CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 11

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Pin Descriptions
50
49
27
89, 90,
81, 82
94, 93,
86, 85
Analog I/O and Control
Pin
BYTE8/10
EXTFIFO
ENCBYP
OUTA±
OUTB±
INA±
INB±
Name
(continued)
Static control input
TTL levels
Normally wired HIGH
or LOW
Static control input
TTL levels
Normally wired HIGH
or LOW
Static control input
TTL levels
Normally wired HIGH
or LOW
PECL compatible
differential output
PECL compatible
differential input
I/O Characteristics
8/10-bit Parallel Data Size Select.
When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is enabled
(ENCBYP is HIGH), 8-bit DATA characters and 4-bit COMMAND characters are
captured at the TXDATA[7:0] or TXCMD[3:0] inputs (selected by the TXSC/D
input) and passed to the Transmit FIFO (if enabled) and encoder. Received
characters are decoded, passed through the Receive FIFO (if enabled) and
presented at either the RXDATA[7:0] or RXCMD[3:0] outputs and indicated by
the RXSC/D output.
When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is bypassed
(ENCBYP is LOW), the internal data paths are set for 10-bit characters. Each
received character is presented to the Receive FIFO (if enabled) and is passed
to the RXDATA[9:0] outputs.
When set for 10-bit data (BYTE8/10 is LOW) and the encoder is enabled
(ENCBYP is HIGH), 10-bit DATA characters and 2-bit COMMAND characters
are captured at the TXDATA[9:0] or TXCMD[1:0] inputs (selected by the
TXSC/D input) and passed to the Transmit FIFO (if enabled) and encoder.
Received characters are decoded, passed through the Receive FIFO (if
enabled) and presented at either the RXDATA[9:0] or RXCMD[1:0] outputs and
indicated by the RXSC/D output.
When set for 10-bit data (BYTE8/10 is LOW) and the encoder is bypassed
(ENCBYP is LOW), the internal clock data paths are set for 12-bit characters.
Each received character is presented to the Receive FIFO (if enabled) and is
passed to the RXDATA[9:0] and the RXCMD[1:0] outputs.
External FIFO Mode.
EXTFIFO modifies the active state of the RXEN and TXEN inputs and the timing
of the Transmitter and Receiver data buses. When configured for external
FIFOs (EXTFIFO is HIGH), TXEN is assumed to be driven by the empty flag of
an attached CY7C42X5 FIFO, and RXEN is assumed to be driven by the almost
full flag of an attached CY7C42X5 FIFO. In this mode the active data transition
is in the clock following the clock edge that “enables” the data bus.
When not configured for external FIFOs (EXTFIFO is LOW), TXEN is assumed
to be driven as a pipeline register and RXEN is assumed to be driven by a
controller for a pipeline register. In this mode the active data transition is within
the same clock as the clock edge that “enables” the data bus.
EXTFIFO also modifies the output state of the Receive and Transmit FIFO flags.
When configured for external FIFOs (EXTFIFO is HIGH), the Full and Empty
FIFO flags are active HIGH (the Half full flag is always active LOW). When not
configured for external FIFOs (EXTFIFO is LOW), all of the FIFO flags are active
LOW.
Enable Encoder Bypass Mode.
When asserted, both the encoder and decoder are bypassed. Data is trans-
mitted without 4B/5B or 5B/6B encoding (but with NRZI encoding), LSB first.
Received data are presented as parallel characters to the parallel interface
without decoding.
When deasserted, data is passed through both the encoder in the Transmit path
and the decoder in the Receive path.
Differential Serial Data Outputs.
These PECL-compatible differential outputs are capable of driving terminated
transmission lines or commercial fiber-optic transmitter modules. To minimize
the power dissipation of unused outputs, the outputs should be left unconnected
and the associated CURSETA or CURSETB should be connected to V
Differential Serial Data Inputs.
These inputs accept the serial data stream for deserialization and decoding.
Only one serial stream at a time may be fed to the receive PLL to extract the
data content. This stream is selected using the A/B input.
Signal Description
CY7C9689A
Page 11 of 51
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