CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 12

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Pin Descriptions
97
78
100
2
3
5
1
80, 87,
88, 95,
96, 98
76, 79,
83, 84,
91, 92,
99
14, 17,
35, 55,
62, 64
4,11,
13, 15,
26, 37,
38, 39,
52, 57,
63, 66
Power
Pin
CURSETA
CURSETB
CARDET
A/B
LFI
DLB
TEST
V
V
V
V
DDA
SSA
DD
SS
Name
(continued)
Analog
Analog
PECL input,
asynchronous
Asynchronous TTL
input
TTL output, changes
following RXCLK↑
Asynchronous TTL
input
Asynchronous TTL
input normally wired
HIGH
I/O Characteristics
Current-set Resistor Input for OUTA±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTA± differential driver.
Current-set Resistor Input for OUTB±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTB± differential driver.
Carrier Detect Input.
Used to allow an external device to signify a valid signal is being presented to
the high-speed PECL input buffers, as is typical on an Optical Module. When
CARDET is deasserted LOW, the LFI indicator asserts LOW signifying a Link
Fault. This input can be tied HIGH for copper media applications.
Input A or Input B Selector.
When HIGH, input INA± is selected, when LOW, INB± is selected.
Link Fault Indication Output. Active LOW.
LFI changes synchronous with RXCLK. This output is driven LOW when the
serial link currently selected by A/B is not suitable for data recovery. This could
be because:
Serial Data Amplitude is below acceptable levels
Input transition density is not sufficient for PLL clock recovery
Input Data stream is outside an acceptable frequency range of operation
CARDET is LOW
Diagnostic Loop Back Selector.
When DLB is LOW, LOOP Mode is OFF. Output of the transmitter shifter is
routed to both OUTA± and OUTB± and the serial input selected by A/B is routed
to the receive PLL for data recovery.
When DLB is HIGH, Diagnostic Loopback is Enabled. Output of the transmitter
serial data is routed to the receive PLL for data recovery. Primarily used for
System Diagnostic test. The serial inputs are ignored and OUTA± and OUTB±
are both active.
Test Mode Select.
Used to force the part into a diagnostic test mode used for factory ATE test. This
input must be tied HIGH during normal operation.
Power for PECL-compatible I/O signals and internal circuits.
Ground for PECL-compatible I/O signals and internal circuits.
Power for TTL I/O signals and internal circuits.
Ground for TTL I/O signals and internal circuits.
Signal Description
CY7C9689A
Page 12 of 51
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