CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 18

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI (Link Fault Indicator) output, which changes
synchronous to RXCLK. While link status is monitored inter-
nally at all times, it is necessary to have transitions on RXCLK
to allow this signal to change externally.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
the received serial stream is performed within the Clock/Data
Recovery (CDR) block. The clock extraction function is
performed by a high-performance embedded PLL that tracks
the frequency of the incoming bit stream and aligns the phase
of its internal bit-rate clock to the transitions in the serial data
stream.
The CDR makes use of the clock present at the REFCLK input.
It is used to ensure that the VCO (within the CDR) is operating
at the correct frequency (rather than some harmonic of the bit
rate), to improve PLL acquisition time, and to limit unlocked
frequency excursions of the CDR VCO when no data is
present at the serial inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits for the range
controls, the CDR PLL will track REFCLK instead of the data
stream. When the frequency of the selected data stream
returns to a valid frequency, the CDR PLL is allowed to track
the received data stream. The frequency of REFCLK is
required to be within ±400 ppm of the frequency of the clock
that drives the REFCLK signal at the remote transmitter to
ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle
selection of the INA± and INB± inputs through the A/B input.
When a port switch takes place, it is necessary for the PLL to
reacquire the new serial stream and frame to the incoming
characters.
Clock Divider
This block contains the clock division logic, used to transfer the
data from the Deserializer/Framer to the Decoder once every
character (once every ten or twelve bits) clock. This counter is
free running and generates outputs at the bit-rate divided by
10 (12 when the BYTE8/10 is LOW). When the Receive FIFO
is bypassed, one of these generated clocks is driven out the
RXCLK pin.
Deserializer/Framer
The CDR circuit extracts bits from the serial data stream and
clocks these bits into the Shifter/Framer at the bit-clock rate.
When enabled, the Framer examines the data stream looking
for JK or LM (when BYTE8/10 is LOW) characters at all
possible bit positions. The location of this character in the data
stream is used to determine the character boundaries of all
following characters.
The framer operates in two different modes, as selected by the
RFEN input. When RFEN is asserted (HIGH), the framer is
allowed to reset the internal character boundaries on any
detected JK or LM (when BYTE8/10 is LOW) character.
If RFEN is LOW, the framer is disabled and no changes are
made to character boundaries.
The framer in the CY7C9689A operates by shifting the internal
character position to align with the character clock. This
ensures that the recovered clock does not contain any signif-
icant phase changes/hops during normal operation or framing,
and allows the recovered clock to be replicated and distributed
to other circuits using PLL-based logic elements.
Decoder Block
The decoder logic block performs two primary functions:
decoding the received transmission characters back into Data
and Command Character codes, and comparing generated
BIST patterns with received characters to permit at-speed link
and device testing.
5B/4B, 6B/5B Decoder
The framed parallel output of the Deserializer is passed to the
5B/4B, 6B/5B Decoder. If the Decoder is enabled, it is trans-
formed from a 10-bit or 12-bit transmission character back to
the original Data and Command Character codes. This block
uses the standard decoder patterns in
this data sheet. Data Patterns on the data bus are indicated by
a LOW on RXSC/D, and Command Character codes on the
command bus are indicated by a HIGH. Invalid patterns or disparity
errors are signaled as errors by a HIGH on VLTN.
If the Decoder is bypassed and BYTE8/10 is HIGH, the ten
(10) data bits of each transmission character are passed
unchanged from the framer to the Pipeline Register.
When the Decoder is bypassed and BYTE8/10 is LOW, the
twelve (12) data bits of each transmission character are
passed unchanged from the framer to the Pipeline Register.
BIST LFSR
The output register of the Decoder block is normally used to
accumulate received characters for delivery to the Receive
Formatter block. When configured for BIST mode (RXBISTEN
is LOW), this register becomes a signature pattern generator
and checker by logically converting to a Linear Feedback Shift
Register (LFSR). When enabled, this LFSR generates a
511-character sequence that includes all Data and Command
Character codes, including the explicit violation symbols. This
provides a predictable but pseudo-random sequence that can
be matched to an identical LFSR in the Transmitter. When
synchronized with the received data stream, it checks each
character in the Decoder with each character generated by the
LFSR and indicates compare errors at the VLTN output of the
Receive Output Register.
The LFSR is initialized by the BIST hardware to the BIST loop
start code of HEX data 00 (00 is sent only once per BIST loop).
Once the start of the BIST loop has been detected by the
receiver, RXRVS is asserted for pattern mismatches between
the received characters and the internally generated character
sequence. Code rule violations or running disparity errors that
occur as part of the BIST loop do not cause an error indication.
RXFULL pulses asserted for one RXCLK cycle per BIST loop and
can be used to check test pattern progress.
The specific patterns checked by the receiver are described in
Table
4.
Table 7
CY7C9689A
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and
Table 8
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