CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 36

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
CY7C9689A TAXI HOTLink Transmit-Path
Operating Mode Descriptions
The TAXI HOTLink Transmitter can be configured into several
operating modes, each providing different capabilities and
fitting different transmission needs. These modes are selected
using the FIFOBYP, ENCBYP and BYTE8/10 inputs on the
CY7C9689A Transceiver. These modes can be reduced to five
primary classes:
Synchronous Encoded
In this mode, the Transmit FIFO is bypassed, while the 4B/5B,
5B/6B encoder is enabled. One character is accepted at the
Transmit Input Register at the rising edge of REFCLK, and
passed to the Encoder where it is encoded for serial trans-
mission. The Serializer operates synchronous to REFCLK,
which is multiplied by 10 or 5 to generate the serial data
bit-clock. In this mode the TXRST and TXHALT inputs are not
interpreted and may be tied either HIGH or LOW. To place the
CY7C9689A into synchronous modes, FIFOBYP must be
LOW.
This mode is usually used for products that must meet specific
predefined protocol requirements, and cannot tolerate the
uncontrolled insertion of SYNC fill characters. The host
system is required to provide new data at every rising edge of
REFCLK (along with TXEN) to maintain the data stream. If
TXEN is not asserted, the Encoder is loaded with JK or LM
sync characters.
Input Register Mapping
In Encoded modes, the bits of the TXDATA input bus are
mapped into characters (as shown in
TXSVS bit, eight bits of data, and a TXSC/D bit to select either
Special Character codes or Data characters.
The TXSC/D bit controls the encoding of the TXDATA[7:0] or
TXDATA[9:0] bits of each character. It is used to identify if the
input character represents a Data Character or a Special
Character code. If TXSC/D is LOW, the character appeared on
the TXDATA bus is encoded using the Data Character codes
listed in
TXCMD bus is encoded using the Special Character codes
listed in
Synchronous Pre-encoded
In synchronous pre-encoded mode, both the Transmit FIFO
and the 4B/5B encoder are bypassed, and data passes directly
from the Transmit Input Register to the Serializer. The
Serializer operates synchronous to REFCLK, which is multi-
plied by 10 or 5 when BYTE8/10 is HIGH (as selected by the
SPDSEL and RANGESEL inputs) to generate the serial data
bit-clock. In this mode, part of the TXCMD bus inputs are used
as part of the data input bus. To place the CY7C9689A into
synchronous modes, FIFOBYP must be LOW.
This mode is usually used for products containing external
encoders or scramblers, that must meet specific protocol
• Synchronous Encoded
• Synchronous Pre-encoded
• Asynchronous Encoded
• Asynchronous Pre-encoded.
Table
Table
8.
7. If TXSC/D is HIGH, the character on the
Table
1), including a
requirements. The host system is required to provide new data
at every rising edge of the REFCLK (along with TXEN) to
maintain the data stream. If TXEN is not asserted, the
Serializer is loaded with JK or LM sync characters.
In this mode the LSB of each input character (TXDATA[0]) is
shifted out first, followed sequentially by TXDATA[1] through
TXDATA[9] (TXDATA[11] when BYTE8/10 is LOW).
Asynchronous Encoded
In Asynchronous Encoded mode, both the Transmit FIFO and
the Encoder are enabled. This provides 256 characters of data
buffering. The Serializer operates synchronous to REFCLK,
which is multiplied by 2.5, 5, or 10 to generate the serial data
bit-clock (as selected by SPDSEL and RANGESEL). In this
mode the TXRST and TXHALT inputs are interpreted.
This mode supports the same Input Register mapping as
Synchronous Encoded mode. Because both the Transmit
FIFO and Encoder are enabled, the input FIFO may be loaded
at any rate supported by the FIFO (up to 50 MHz), without
generating any decoder errors at the receive end of the link.
CY7C9689A TAXI HOTLink Receive-Path
Operating Mode Descriptions
The HOTLink Receiver can be configured into several
operating modes, each providing different capabilities and
fitting different reception needs. These modes are selected
using the FIFOBYP, ENCBYP, BYTE8/10 inputs on the
CY7C9689A Transceiver. These modes can be reduced to
four primary classes:
In all these modes, serial data is received at one of the differ-
ential line receiver inputs and routed to the Deserializer and
Framer. The PLL in the clock and data recovery block is used
to extract a bit-rate clock from the transitions in the data
stream, and uses that clock to capture bits from the serial
stream. These bits are passed to the Deserializer where they
are formed into 10- or 12-bit characters.
To align the incoming bit stream to the proper character bound-
aries, the Framer must be enabled by asserting RFEN HIGH.
The Framer logic-block checks the incoming bit stream for the
unique pattern that defines the character boundaries. This
logic filter looks for the JK or LM (when BYTE8/10 is LOW)
sync character. Once a sync character is found, the Framer
captures the offset of the data stream from the present
character boundaries, and resets the boundary to reflect this
new offset, thus framing the data to the correct character
boundaries.
Since noise induced errors can cause the incoming data to be
corrupted, and since many combinations of corrupt and legal
data can create an aliased sync character, the framer may also
be disabled by deasserting RFEN LOW.
Synchronous Decoded
In these modes, the Receive FIFO is bypassed, while the
5B/4B, 6B/5B Decoder is enabled. Framed characters output
from the Deserializer are decoded, and passed directly to the
• Synchronous Decoded
• Synchronous Undecoded
• Asynchronous Decoded
• Asynchronous Undecoded.
CY7C9689A
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