PIC18F67K90-E/PT Microchip Technology, PIC18F67K90-E/PT Datasheet - Page 210
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PIC18F67K90-E/PT
Manufacturer Part Number
PIC18F67K90-E/PT
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F67K90-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K90-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K90 FAMILY
15.6
The TMRx register pair (TMRxH:TMRxL) increments
from 0000h to FFFFh and overflows to 0000h. The
Timerx interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMRxIF.
Table 15-3
TABLE 15-3:
This interrupt can be enabled or disabled by setting or
clearing the TMRxIE bit, respectively.
each module’s enable bit.
TABLE 15-4:
DS39957D-page 210
Timer Module
Timer Module
3
5
7
3
5
7
Timer3/5/7 Interrupt
gives each module’s flag bit.
TIMER3/5/7 INTERRUPT
FLAG BITS
TIMER3/5/7 INTERRUPT
ENABLE BITS
PIR2<1>
PIR5<1>
PIR5<3>
PIE2<1>
PIE5<1>
PIE5<3>
Flag Bit
Flag Bit
Table 15-4
gives
15.7
If the ECCP modules are configured to use Timerx and
to generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timerx. The
trigger from ECCP2 will also start an A/D conversion if
the A/D module is enabled. (For more information, see
Section 19.3.4 “Special Event
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timerx.
If Timerx is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timerx coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Note:
Note:
Resetting Timer3/5/7 Using the
ECCP Special Event Trigger
The Special Event Triggers from the
ECCPx module will only clear the TMR3
register’s content, but not set the TMR3IF
interrupt flag bit (PIR1<0>).
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see
Register 18-2
2009-2011 Microchip Technology Inc.
and
Register
Trigger”.)
Register
18-3.
19-2,
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