PIC18F67K90-E/PT Microchip Technology, PIC18F67K90-E/PT Datasheet - Page 306
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K90-E/PT
Manufacturer Part Number
PIC18F67K90-E/PT
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F67K90-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K90-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 306 of 570
- Download datasheet (5Mb)
successfully.
PIC18F87K90 FAMILY
21.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a Transmit/Receive
Shift register (SSPxSR) and a Serial Receive Transmit
Buffer register (SSPxBUF). The SSPxSR shifts the
data in and out of the device, MSb first. The SSPxBUF
holds the data that was written to the SSPxSR until the
received data is ready. Once the 8 bits of data have
been received, that byte is moved to the SSPxBUF
register. Then, the Buffer Full detect bit, BF
(SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are
set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPxBUF register during transmission/reception of data
will be ignored and the Write Collision Detect bit, WCOL
(SSPxCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s)
EXAMPLE 21-1:
DS39957D-page 306
LOOP
output time)
SCKx)
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
to
OPERATION
the
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
SSPxBUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
register
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
completed
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
loading
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
21.3.3
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, and allows the output to communicate with
external circuits without the need for additional level
shifters. For more information, see
“Open-Drain
The open-drain output option is controlled by the
SSP2OD
(ODCON1<7>). Setting an SSPxOD bit configures the
SDOx and SCKx pins for the corresponding module for
open-drain operation.
Note:
of
OPEN-DRAIN OUTPUT OPTION
To avoid lost data in Master mode, a
read of the SSPxBUF must be per-
formed to clear the Buffer Full (BF)
detect bit (SSPxSTAT<0>) between
each transmission.
(ODCON1<0>)
the
Outputs”.
2009-2011 Microchip Technology Inc.
SSPxBUF
Example 21-1
and
(SSPxSR)
SSP1OD
Section 11.1.3
shows the
for
data
bits
Related parts for PIC18F67K90-E/PT
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![TC1014-2.7VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1014-5.0VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.5VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.7VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.8VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-4.0VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1186-2.5VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1186-2.85VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet: