PIC18F67K90-E/PT Microchip Technology, PIC18F67K90-E/PT Datasheet - Page 67
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K90-E/PT
Manufacturer Part Number
PIC18F67K90-E/PT
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F67K90-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K90-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-4:
2009-2011 Microchip Technology Inc.
Note 1:
2:
3:
4:
5:
Power-Managed
SEC_IDLE mode
PRI_IDLE mode
RC_IDLE mode
Sleep mode
T
runs concurrently with any other required delays (see
Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
T
(Parameter F12,
Execution continues during T
The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
CSD
OST
Mode
(Parameter 38,
is the Oscillator Start-up Timer (Parameter 32,
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Table
Table
31-7); it is also designated as T
31-10) is a required delay when waking from Sleep and all Idle modes, and
IOBST
Clock Source
MF-INTOSC
MF-INTOSC
MF-INTOSC
HF-INTOSC
HF-INTOSC
HF-INTOSC
LF-INTOSC
LF-INTOSC
LF-INTOSC
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
HSPLL
HSPLL
(Parameter 39,
SOSC
(2)
(2)
(2)
(2)
(2)
(2)
(5)
PIC18F87K90 FAMILY
Table
Table
Section 4.4 “Idle
PLL
31-10), the INTOSC stabilization period.
.
31-10). T
T
Exit Delay
OST
T
T
T
T
T
T
IOBST
CSD
CSD
CSD
OST
CSD
RC
+ t
(1)
(1)
(1)
(3)
(1)
rc
is the PLL Lock-out Timer
(4)
(3)
Modes”).
Clock Ready
Status Bits
SOSCRUN
DS39957D-page 67
MFIOFS
HFIOFS
MFIOFS
HFIOFS
HFIOFS
MFIOFS
OSTS
OSTS
None
None
None
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