PIC18F85J50T-I/PT Microchip Technology, PIC18F85J50T-I/PT Datasheet - Page 143
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PIC18F85J50T-I/PT
Manufacturer Part Number
PIC18F85J50T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F65J50-IPT.pdf
(480 pages)
3.PIC18F65J50-IPT.pdf
(16 pages)
Specifications of PIC18F85J50T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
I2C, MSSP, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
65
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F85J50T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F85J50T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 143 of 480
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10.3
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins
(of RB7:RB4) are compared with the old value latched
on the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a)
b)
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
© 2009 Microchip Technology Inc.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Clear flag bit, RBIF.
interrupt
PORTB, TRISB and
LATB Registers
can
wake
the
device
from
PIC18F87J50 FAMILY
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB<3>
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
EXAMPLE 10-2:
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
INITIALIZING PORTB
DS39775C-page 143
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