DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 2

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

1 0 CONNECTION DIAGRAMS
2 0 PIN DESCRIPTION
3 0 FUNCTIONAL DESCRIPTION
4 0 TRANSMIT RECEIVE IEEE 802 3 FRAME FORMAT
5 0 BUFFER MANAGEMENT
1 1 Pin Connection Diagram National Intel Mode
1 2 Pin Connection Diagram Motorola Mode
3 1 Twisted Pair Interface Module
3 2 IEEE 802 3 Encoder Decoder (ENDEC) Unit
3 3 Media Access Control (MAC) Unit
3 4 Data Width and Byte Ordering
3 5 FIFO and Control Logic
3 6 Status and Configuration Registers
3 7 Bus Interface
3 8 Loopback and Diagnostics
3 9 Network Management Functions
4 1 Preamble and Start of Frame Delimiter (SFD)
4 2 Destination Address
4 3 Source Address
4 4 Length Type Field
4 5 Data Field
4 6 FCS Field
4 7 MAC (Media Access Control) Conformance
5 1 Buffer Management Overview
5 2 Descriptor Areas
5 3 Descriptor Data Alignment
5 4 Receive Buffer Management
3 2 1 ENDEC Operation
3 2 2 Selecting an External ENDEC
3 3 1 MAC Receive Section
3 3 2 MAC Transmit Section
3 5 1 Receive FIFO
3 5 2 Transmit FIFO
3 8 1 Loopback Procedure
5 2 1 Naming Convention for Descriptors
5 2 2 Abbreviations
5 2 3 Buffer Management Base Addresses
5 4 1 Receive Resource Area (RRA)
5 4 2 Receive Buffer Area (RBA)
5 4 3 Receive Descriptor Area (RDA)
5 4 4 Receive Buffer Management Initialization
5 4 5 Beginning of Reception
5 4 6 End of Packet Processing
5 4 7 Overflow Conditions
Table of Contents
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6 0 SONIC-T REGISTERS
7 0 BUS INTERFACE
8 0 NETWORK INTERFACING
9 0 AC AND DC SPECIFICATIONS
10 0 AC TIMING TEST CONDITIONS
5 5 Transmit Buffer Management
6 1 The CAM Unit
6 2 Status Control Registers
6 3 Register Description
7 1 Pin Configurations
7 2 System Configuration
7 3 Bus Operations
8 1 Manchester Encoder and Differential Driver
8 2 Twisted Pair Interface Module
5 5 1 Transmit Descriptor Area (TDA)
5 5 2 Transmit Buffer Area (TBA)
5 5 3 Preparing to Transmit
5 5 4 Dynamically Adding TDA Descriptors
6 1 1 The Load CAM Command
6 3 1 Command Register
6 3 2 Data Configuration Register
6 3 3 Receive Control Register
6 3 4 Transmit Control Register
6 3 5 Interrupt Mask Register
6 3 6 Interrupt Status Register
6 3 7 Data Configuration Register 2
6 3 8 Transmit Registers
6 3 9 Receive Registers
6 3 10 CAM Registers
6 3 11 Tally Counters
6 3 12 General Purpose Timer
6 3 13 Silicon Revision Register
7 3 1 Acquiring the Bus
7 3 2 Block Transfers
7 3 3 Bus Status
7 3 4 Bus Mode Compatibility
7 3 5 Master Mode Bus Cycles
7 3 6 Bus Exceptions (Bus Retry)
7 3 7 Slave Mode Bus Cycle
7 3 8 On-Chip Memory Arbiter
7 3 9 Chip Reset
8 1 1 Manchester Decoder
8 1 2 Collision Translator
8 1 3 Oscillator Inputs
8 1 4 Power Supply Considerations