DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 9

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

BUS INTERFACE PINS (BOTH BUS MODES) (Continued)
SHARED-MEMORY ACCESS PINS
BUS INTERFACE PINS (NATIONAL INTEL MODE BMODE
Symbol
SAS
DS
BRT
ECS
MREQ
SMACK
ADS
MWR
INT
HOLD
HLDA
BGACK
SWR
RDYi
RDYo
2 0 Pin Description
Driver
Type
TRI
TRI
TRI
TRI
TRI
TP
TP
TP
TP
Direction
O Z
O Z
O Z
O Z
O Z
O
O
O
O
I
I
I
I
I
I
SLAVE ADDRESS STROBE The system asserts this pin to latch the register address on lines
RA0–RA5
DATA STROBE When the SONIC-T is bus master it drives this pin low during a read cycle to
indicate that the slave device may drive data onto the bus in a write cycle this pin indicates that
the SONIC-T has placed valid data onto the bus
BUS RETRY When the SONIC-T is bus master the system asserts this signal to rectify a
potentially correctable bus error This pin has two modes Mode 1 (the LBR in the Data
Configuration Register is set to 0) Assertion of this pin forces the SONIC-T to terminate the
current bus cycle and will repeat the same cycle after BRT has been deasserted Mode 2 (the
LBR bit in the Data Configuration register is set to 1) Assertion of this signal forces the SONIC-T
to retry the bus operation as in Mode 1 However the SONIC-T will not continue DMA operations
until the BR bit in the ISR is reset
EARLY CYCLE START This output gives the system earliest indication that a memory operation
is occurring This signal is driven low at the rising edge of T1 and high at the falling edge of T1
MEMORY REQUEST The system asserts this signal low when it attempts to access the shared-
buffer RAM The on-chip arbiter resolves accesses between the system and the SONIC-T
Note Both CS and MREQ must not be asserted concurrently If these signals are successively
asserted there must be at least two bus clocks between the deasserting edge of the first signal
and the asserting edge of the second signal
SLAVE AND MEMORY ACKNOWLEDGE SONIC-T asserts this dual function pin low in response
to either a Chip Select (CS) or a Memory Request (MREQ) when the SONIC-T’s registers or its
buffer memory is available for accessing This pin can be used for enabling bus drivers for dual-
bus systems
ADDRESS STROBE (ADS) The rising edge indicates valid status and address
MEMORY WRITE READ STROBE MWR When the SONIC-T has acquired the bus this signal
indicates the direction of the data transfer The signal is low during a read cycle and high during a
write cycle
INTERRUPT (INT) Indicates that an interrupt (if enabled) is pending from one of the sources
indicated by the Interrupt Status register Interrupts that are disabled in the Interrupt Mask register
will not activate this signal
HOLD REQUEST (HOLD) The SONIC-T drives this pin high when it intends to use the bus and is
driven low when inactive
HOLD ACKNOWLEDGE (HLDA) This signal is used to inform the SONIC-T that it has attained
the bus When the system asserts this pin high the SONIC-T has gained ownership of the bus
BUS GRANT ACKNOWLEDGE This pin is only used when BMODE
SLAVE READ WRITE STROBE (SWR) The system asserts this pin to indicate whether it will
read from or write to the SONIC-T’s registers This signal is asserted low during a read and high
during a write
READY INPUT (RDYi BMODE
signal high to insert wait-states and low to terminate the memory cycle This signal is sampled
synchronously or asynchronously depending on the state of the SBUS bit (See Sections 7 3 5
and 6 3 2 for details )
READY OUTPUT (RDYo) When a register is accessed the SONIC-T asserts this signal to
terminate the slave cycle
(Continued)
TABLE 2-1 Pin Description (Continued)
e
0)
9
e
0) When the SONIC-T is a bus master the system asserts this
Description
e
1