DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 60

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

7 0 Bus Interface
7 3 5 Master Mode Bus Cycles
In order to add additional compatibility with different bus
architectures there are two other modes that affect the op-
eration of the bus These modes are called the synchronous
and asynchronous modes and are programmed by setting
or resetting the SBUS bit in the Data Configuration Register
(DCR) The synchronous and asynchronous modes do not
have an effect on slave accesses to the SONIC-T but they
do affect the master mode operation Within the particular
bus processor mode
modes are very similar This section discusses all four
modes of operation of the SONIC-T (National Intel vs
Motorola synchronous vs asynchronous) when it is a bus
master
In this section the rising edge of T1 and T2 means the
beginning of these states and the falling edge of T1 and T2
means the middle of these states
7 3 5 1 Adding Wait States
To accommodate different memory speeds the SONIC-T
provides two methods for adding wait states for its bus op-
erations Both of these methods can be used singly or in
conjunction with each other A memory cycle is extended by
adding additional T2 states The first method inserts wait-
states by withholding the assertion of DSACK0 1 STERM or
RDYi The other method allows software to program wait-
states Programming the WC0 WC1 bits in the Data Config-
uration Register allows 1 to 3 wait-states to be added on
each memory cycle These wait states are inserted between
the T1 and T2 bus states and are called T2 (wait) bus
states The SONIC-T will not look at the DSACK0 1 STERM
or RDYi lines until the programmed wait states have
passed Hence in order to complete a bus operation that
synchronous and asynchronous
FIGURE 7-6 Memory Read BMODE
(Continued)
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includes programmed wait states the DSACK0 1 STERM
or RDYi lines must be asserted at their proper times at the
end of the cycle during the last T2 not during a pro-
grammed wait state The only exception to this is asynchro-
nous mode where DSACK0 1 or RDYi would be asserted
during the last programmed wait state T2 (wait) See the
timing for these signals in the timing diagrams for more spe-
cific information Programmed wait states do not affect
Slave Mode bus cycles
7 3 5 2 Memory Cycle for BMODE
Synchronous Mode
On the rising edge of T1 the SONIC-T asserts ECS to indi-
cate that the memory cycle is starting The address (A31–
A1) bus status (S2 – S0) and the direction strobe (MRW) are
driven and do not change for the remainder of the memory
cycle On the falling edge of T1 the SONIC-T deasserts
ECS and asserts AS
In synchronous mode DSACK0 1 are sampled on the rising
edge of T2 T2 states will be repeated until DSACK0 1 are
sampled properly in a low state DSACK0 1 must meet the
setup and hold times with respect to the rising edge of bus
clock for proper operation
During read cycles (Figure 7-6) data (D31– D0) is latched at
the falling edge of T2 and DS is asserted at the falling edge
of T1 For write cycles (Figure 7-7) data is driven on the
falling edge of T1 If there are wait states inserted DS is
asserted on the falling edge of T2 DS is not asserted for
zero wait state write cycles The SONIC-T terminates the
memory cycle by deasserting AS and DS at the falling edge
of T2
1 Synchronous (1 Wait-State)
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