SAA7118H NXP Semiconductors, SAA7118H Datasheet - Page 22

• Manufacturer Part Number: SAA7118H
• Manufacturer: NXP Semiconductors

Specifications of SAA7118H

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7118_7
Product data sheet
8.1.2.1 Chrominance path
The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature
demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the
subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis).
The frequency is dependent on the chosen color standard.
The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1).
Eight characteristics are programmable via LCBW2 to LCBW0 to achieve the desired
bandwidth for the color difference signals (PAL and NTSC) or the 0 and 90 FM signals
(SECAM).
The chrominance low-pass 1 characteristic also influences the grade of cross luminance
reduction during horizontal color transients (large chrominance bandwidth means strong
suppression of cross luminance). If the Y-comb filter is disabled by YCOMB = 0 the filter
influences directly the width of the chrominance notch within the luminance path (a large
chrominance bandwidth means wide chrominance notch resulting in a lower luminance
bandwidth).
The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance
components are separated from the luminance via a two-line vertical stage (four lines for
PAL standards) and a decision logic between the filtered and the non-filtered output
signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled
independently for the succeeding luminance and chrominance processing by YCOMB
(subaddress 09h, bit D6) and/or CCOMB (subaddress 0Eh, bit D0). It is always bypassed
during VBI or raw data lines programmable by the LCRn registers (subaddresses
41h to 57h); see
The separated C
(low-pass 2) to modify the chrominance bandwidth without influencing the luminance
path. Its characteristic is controlled by CHBW (subaddress 10h, bit D3). For the complete
transfer characteristic of low-passes 1 and 2, see
The SECAM processing (bypassed for QAM standards) contains the following blocks:
The succeeding chrominance gain control block amplifies or attenuates the C
according to the required ITU 601/656 levels. It is controlled by the output signal from the
amplitude detection circuit within the burst processing block.
The burst processing block provides the feedback loop of the chrominance PLL and
contains the following:
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•
•
•
•
•
•
Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0 and 90
FM signals
Phase demodulator and differentiator (FM-demodulation)
De-emphasis filter to compensate the pre-emphasized input signal, including
frequency offset compensation (DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM switch signal)
Burst gate accumulator
Color identification and color killer
Comparison nominal/actual burst amplitude (PAL/NTSC standards only)
Loop filter chrominance gain control (PAL/NTSC standards only)
B
Section
-C
R
components are further processed by a second filter stage
Rev. 07 — 7 July 2008
8.3.
Multistandard video decoder with adaptive comb filter
Figure 12
and
Figure
SAA7118
© NXP B.V. 2008. All rights reserved.
13.
B
-C
R
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signal