SAA7118H NXP Semiconductors, SAA7118H Datasheet - Page 67

• Manufacturer Part Number: SAA7118H
• Manufacturer: NXP Semiconductors

Specifications of SAA7118H

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 21.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] LN = line number.
[11] DT = data type according to table.
[12] CNT = counter.
SAA7118_7
Product data sheet
Nick
name
DID,
SAV,
EAV
SDID programmable via
DC
IDI1
IDI2
CS
BC
[8]
NEP = inverted EP; for EP see
EP = even parity of bits D5 to D0.
FID = 0: field 1; FID = 1: field 2.
I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field.
Subaddress 5Dh at 3Eh and 3Fh are used for ITU 656 like SAV/EAV header generation; recommended value.
V = 0: active video; V = 1: blanking.
H = 0: start of line; H = 1: end of line.
DC = data count in double words according to the data type.
OP = odd parity of bits D6 to D0.
Comment
subaddress 5Dh = 00h
subaddress 5Dh D5 = 1
subaddress 5Dh
D5 = 3Eh
subaddress 5Dh
D5 = 3Fh
subaddress 5Eh
check sum byte
valid byte count
Bytes stream of the data slicer
[5]
[5]
8.7 Audio clock generation (subaddresses 30h to 3Fh)
The SAA7118 incorporates the generation of a field-locked audio clock as an auxiliary
function for video capture. An audio sample clock, that is locked to the field frequency,
ensures that there is always the same predefined number of audio samples associated
with a field, or a set of fields. This ensures synchronous playback of audio and video after
digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear
editing.
Table note
D7
NEP
NEP
1
0
NEP
NEP
OP
OP
CS6
OP
[9]
[9]
[9]
[1]
[1]
[1]
[1]
2.
D6
EP
EP
FID
FID
EP
EP
FID
LN2
CS6
0
[2]
[2]
[2]
[2]
[3]
[3]
[3]
[10]
Rev. 07 — 7 July 2008
D5
0
0
V
V
D5[5Eh]
DC5
LN8
LN1
CS5
CNT5
[6]
[6]
Multistandard video decoder with adaptive comb filter
[10]
[10]
[12]
D4
1
D4[5Dh]
H
H
D4[5Eh]
DC4
LN7
LN0
CS4
CNT4
[7]
[7]
[10]
[10]
[12]
D3
0
D3[5Dh]
P3
P3
D3[5Eh]
DC3
LN6
DT3
CS3
CNT3
[10]
[11]
[12]
D2
FID
D2[5Dh]
P2
P2
D2[5Eh]
DC2
LN5
DT2
CS2
CNT2
[3]
[10]
[11]
[12]
D1
I1
D1[5Dh]
P1
P1
D1[5Eh]
DC1
LN4
DT1
CS1
CNT1
SAA7118
© NXP B.V. 2008. All rights reserved.
[4]
[10]
[11]
[12]
D0
I0
D0[5Dh]
P0
P0
D0[5Eh]
DC0
LN3
DT0
CS0
CNT0
[4]
67 of 177
[10]
[11]
[12]