SAA7118H NXP Semiconductors, SAA7118H Datasheet - Page 58
SAA7118H
Manufacturer Part Number
SAA7118H
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7118H.pdf
(177 pages)
Specifications of SAA7118H
Adc/dac Resolution
9b
Screening Level
Commercial
Package Type
PQFP
Pin Count
160
Lead Free Status / RoHS Status
Compliant
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SAA7118H/V1
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SAA7118_7
Product data sheet
Fig 39. Basic problem of interlaced vertical scaling (example: downscale
field 1
8.4.3.3 Use of the vertical phase offsets
unscaled input
scale dependent start offset
As described in
interlaced input sequence. Additionally the interpretation and timing between ITU 656 field
ID and real-time detection by means of the state of H-sync at the falling edge of V-sync
may result in different field ID interpretation.
A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the
interlaced input fields are processed, without regard to the actual scale at the starting
point of operation
For correct interlaced processing the vertical scaler must be used with respect to the
interlace properties of the input signal and, if required, for conversion of the field
sequences.
Four events should be considered, they are illustrated in
field 2
Section
Figure
field 1
Rev. 07 — 7 July 2008
8.4.1.3, the scaler processing may run randomly over the
no phase offset
39.
scaled output,
mismatched vertical line distances
Multistandard video decoder with adaptive comb filter
field 2
3
field 1
5
)
with phase offset
scaled output,
correct scale dependent position
Figure
40.
field 2
SAA7118
© NXP B.V. 2008. All rights reserved.
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