NAND256W3A2BN6F NUMONYX, NAND256W3A2BN6F Datasheet - Page 20

• Manufacturer Part Number: NAND256W3A2BN6F
• Manufacturer: NUMONYX

Specifications of NAND256W3A2BN6F

• Cell Type: NAND
• Density: 256Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 32M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Bus operations
4.4
4.5
4.6
20/59
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See
characteristics for operations
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, therefore, the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
Standby
When Chip Enable is High the memory enters standby mode: the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. A8 is set Low or High by the 00h or 01h command (see
2. Any additional address input cycles are ignored.
Command input
Bus operation
Cycle
Address input
Bus
Write protect
2
3
1
Data output
Data input
nd
Figure 24: Sequential data output after read AC waveforms
rd
st
Standby
Bus operations
Address insertion, x8 devices
I/O7
A16
A24
A7
IH
when issuing a program or erase command.
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
I/O6
A15
A23
A6
V
AL
V
V
V
X
X
IH
IL
IL
IL
for details of the timings requirements.
I/O5
A14
A22
A5
V
CL
V
V
V
X
X
IH
IL
IL
IL
Falling
V
V
V
R
X
X
I/O4
A13
A21
IH
IH
IH
A4
(1)(2)
Section 6.1: Pointer
Rising
Rising
Rising
V
W
X
X
IH
I/O3
A12
A20
A3
WP
X
V
X
X
X
X
(2)
IL
I/O2
A11
A19
and
operations).
A2
NAND128-A, NAND256-A
Data output
I/O0 - I/O7
Command
Data input
Address
Table 20: AC
X
X
I/O1
A10
A18
A1
I/O8 - I/O15
Data output
Data input
X
X
X
X
I/O0
A17
A0
A9
(1)