NAND256W3A2BN6F NUMONYX, NAND256W3A2BN6F Datasheet - Page 57

• Manufacturer Part Number: NAND256W3A2BN6F
• Manufacturer: NUMONYX

Specifications of NAND256W3A2BN6F

• Cell Type: NAND
• Density: 256Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 32M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

NAND128-A, NAND256-A
13
Revision history
Table 24.
28-May-2004
07-Aug-2003
03-Dec-2003
03-Dec-2004
06-Jun-2003
27-Oct-2003
13-Apr-2004
01-Oct-2004
02-Jul-2004
Date
Document revision history
Version
1
2
3
4
5
6
7
8
9
Initial release
Design phase
Engineering phase
Document promoted from Target Specification to Preliminary Data status.
V
Changed title of
timing for NANDXXXR3A devices corrected.
NAND256-A device
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm)
removed.
Figure 19: Cache Program
removed for t
address, data
t
characteristics for
References removed from
reference made to ST website instead.
Figure 5: VFBGA55 connections, x8 devices (top view through
Figure 6: VFBGA55 connections, x16 devices (top view through
package),
Figure 30: Block erase AC waveform
electronic signature
waveform, modified. Note 2 to
waveform
program operation. Note added to
Small text changes.
TFBGA55 package added (mechanical data to be announced). 512-Mbit
dual die devices added.
Package code changed for TFBGA63 8.5 x 15 x 1.2 mm, 6x8 ball array,
0.8 mm pitch (1-Gbit dual die devices) in
scheme.
Cache Program removed from document. TFBGA55 package
specifications added
array - 0.80mm pitch, Package Outline
10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical
Test conditions modified for V
Section 6.5: Block erase
block modified in
added to
Document promoted from Preliminary Data to Full Datasheet status.
Automatic Page 0 Read at power-up option no longer available.
PC Demo board with simulation software removed from list of available
development tools.
WHBH1
CC
changed to V
and t
Section 1:
removed. Only 00h pointer operations are valid before a cache
Figure 27: Page read A/read B operation AC waveform
WHRL
WLWH
input. Meaning of t
Table 2: Product description
Section 7.1: Bad block
DD
operations.
min for 3 V devices modified in
timing in
Section 3.5: Chip Enable (E)
clarified and
Description.
summary, inserted on page 2.
(Figure 40., TFBGA55 8 x 10mm - 6x8 active ball
and I
Figure 19., Cache Program Operation
last address cycle modified. Definition of a bad
CC
Section 13: Revision history
Operation, modified and note 2 modified. Note
Revision details
Table 19: AC characteristics for command,
OL
to I
Figure 28: Read C operation, one page AC
and V
Figure 2: Logic block diagram
DD
Figure 26: Read electronic signature AC
BLBH4
Figure 30: Block erase AC
.
modified.
OH
modified, partly replaced by
and
management. RoHS compliance
Table 23: Ordering information
parameters.
Table 25., TFBGA55 8 x
Table 1: NAND128-A and
and page program typical
Section 6.8: Read
paragraph clarified.
Table 20: AC
Revision history
section and
waveform.
package),
modified.
modified.
and
Data).
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