FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 136

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.10.2
5.10.3
5.10.4
136
Table 51. Stop Frame Explanation
Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames
based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1
clock each:
Stop Frame
After all data frames, a Stop Frame is driven by the ICH5. The SERIRQ signal is driven low by the
ICH5 for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration
register. The number of clocks determines the next mode:
Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream that are not supported by the ICH5. These
interrupts are generated internally, and are not sharable with other devices within the system. These
interrupts are:
The ICH5 ignores the state of these interrupts in the serial stream, and does not adjust their level
based on the level seen in the serial stream. In addition, the interrupts IRQ14 and IRQ15 from the
serial stream are treated differently than their ISA counterparts. These two frames are not passed to
the Bus Master IDE logic. The Bus Master IDE logic expects IDE to be behind the ICH5.
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Stop Frame Width
Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ
devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors
(there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A
low level during the IRQ0
not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame
indicates that an active-low interrupt is being requested.
Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample
Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.
Turn-around Phase. The device tri-states the SERIRQ line
IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
IRQ8#. RTC interrupt can only be generated internally.
IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#.
2 PCI clocks
3 PCI clocks
Quiet Mode. Any SERIRQ device may initiate a Start Frame
Continuous Mode. Only the host (Intel
–
1 and IRQ2
–
15 frames indicates that an active-high ISA interrupt is
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Next Mode
®
ICH5) may initiate a Start Frame