FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 383

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

9.8.9
9.8.10
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register
for Devices 4–7 (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
These registers set the ranges that Device Monitors 4
Monitor 4. Offset C6h corresponds to Monitor 5, etc.
If the trap is enabled in the MON_SMI register and the address is in the trap range (and passes the
mask set in the MON_TRP_MSK register), the ICH5 will generate an SMI#. This SMI# occurs if
the address is positively decoded by another device on PCI or by the ICH5 (because it would be
forwarded to LPC or some other ICH5 internal registers). The trap ranges should not point to
registers in the ICH5’s internal IDE, USB, AC ’97 or LAN I/O space. If the cycle is to be claimed
by the ICH5 and targets one of the permitted ICH5 internal registers (interrupt controller, RTC,
etc.), the cycle will complete to the intended target and an SMI# will be generated (this is the same
functionality as the ICH component). If the cycle is to be claimed by the ICH5 and the intended
target is on LPC, an SMI# will be generated but the cycle will only be forwarded to the intended
target if forwarding to LPC is enabled via the TRP_FWD_EN register settings.
MON_TRP_MSK—I/O Monitor Trap Range Mask Register
for Devices 4–7 (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
15:12
15:0
11:8
Bit
Bit
7:4
3:0
MON[ n ]_TRAP_BASE — R/W. Base I/O locations that MON[n] traps (where n = 4, 5, 6 or 7). The
range can be mapped anywhere in the processor I/O space (0–64 KB).
Any access to the range will generate an SMI# if enabled by the associated DEV[n]_TRAP_EN bit in
the MON_SMI register (PMBASE +40h).
MON7_MASK — R/W. This field selects low 4–bit mask for the I/O locations that MON7 will trap.
Similar to MON4_MASK.
MON6_MASK — R/W. This field selects low 4–bit mask for the I/O locations that MON6 will trap.
Similar to MON4_MASK.
MON5_MASK — R/W. This field selects low 4–bit mask for the I/O locations that MON5 will trap.
Similar to MON4_MASK.
MON4_MASK — R/W. This field selects low 4–bit mask for the I/O locations that MON7 will trap.
When a mask bit is set to a 1, the corresponding bit in the base I/O selection will not be decoded.
For example, if MON4_TRAP_BASE = 1230h, and MON4_MSK = 0011b, the Intel
decode 1230h, 1231h, 1232h, and 1233h for Monitor 4.
C4h, C6h, C8h, CAh
00h
No
Core
CCh
00h
No
Core
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
–
7 should trap. Offset 4Ch corresponds to
R/W
16 bits
Legacy Only
R/W
16 bits
Legacy Only
®
ICH5 will
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