FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 243

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

5.21.2
5.21.3
5.21.3.1
5.21.3.2
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The ICH5 supports the same arbitration protocol for both the SMBus and the System Management
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low
to signal a start condition. The ICH5 must continuously monitor the SMBDATA line. When the
ICH5 is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples
SMBDATA low, then some other master is driving the bus and the ICH5 must stop transferring
data.
If the ICH5 sees that it has lost arbitration, the condition is called a collision. The ICH5 will set the
BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The
processor is responsible for restarting the transaction.
When the ICH5 is a SMBus master, it drives the clock. When the ICH5 is sending address or
command as an SMBus master, or data bytes as a master on writes, it drives data relative to the
clock it is also driving. It will not start toggling the clock until the start or stop condition meets
proper setup and hold time. The ICH5 will also guarantee minimum time between SMBus
transactions as a master.
(SMLINK) interfaces.
Bus Timing
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH5 as an SMBus
master would like. They have the capability of stretching the low time of the clock. When the ICH5
attempts to release the clock (allowing the clock to go high), the clock will remain low for an
extended period of time.
The ICH5 must monitor the SMBus clock line after it releases the bus to determine whether to
enable the counter for the high time of the clock. While the bus is still low, the high time counter
must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if
it is not ready to send or receive data.
Bus Time Out (Intel
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge,
or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH5
will discard the cycle, and set the DEV_ERR bit. The time out minimum is 25 ms. The time-out
counter inside the ICH5 will start after the last bit of data is transferred by the ICH5 and it is
waiting for a response. The 25 ms will be a count of 800 RTC clocks.
®
ICH5 as SMBus Master)
Functional Description
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