PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 24

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The 8031
and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA, have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN,
CNTL2)) and Data memory (selected using Read
Strobe (RD, CNTL1)). Any of the memories within
the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM
register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
Table 11. VM Register
Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate
Modes. Program space is separated from Data
space. For example, Program Select Enable (PS-
EN, CNTL2) is used to access the program code
Figure 7. 8031 Memory Modules – Separate Space
24/95
0 = disable
PIO mode
1= enable
PIO mode
PIO_EN
Bit 7
not used not used
not used not used
Bit 6
DPLD
Bit 5
RD
RS0
CSBOOT0-3
FS0-FS7
PSEN
0 = RD
can’t
access
Flash
memory
1 = RD
access
Flash
memory
FL_Data
Primary
Bit 4
Space
CS
0 = RD can’t
access Secondary
Flash memory
1 = RD access
Secondary Flash
memory
Primary
Memory
Flash
OE
Secondary
EE_Data
Bit 3
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired.
Table 11 describes the VM Register.
from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM register
to be set to 0Ch (see Figure 7).
Secondary
CS
Memory
0 = PSEN
can’t
access
Flash
memory
1 = PSEN
access
Flash
memory
Flash
FL_Code
OE
Primary
Bit 2
0 = PSEN can’t
access Secondary
Flash memory
1 = PSEN access
Secondary Flash
memory
Secondary
EE_Code
CS
SRAM
Bit 1
OE
0 = PSEN
can’t
access
SRAM
1 = PSEN
access
SRAM
SRAM_Code
AI02869C
Bit 0