PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 26

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
Figure 9. Page Register
26/95
in
the
Sector
Select
RESET
R/ W
D 0 - D7
(FS0-FS7,
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
REGISTER
PAGE
Q 0
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 9 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
DPLD
CPLD
AND
PLD
INTERNAL
SELECTS
AND LOGIC
AI02871B