PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 38

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Table
14. The interface type is specified using the PSD-
soft Express Configuration.
PSD Interface to a Multiplexed 8-Bit Bus. Fig-
ure 16 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
Table 14. MCUs and their Control Signals
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
38/95
8031
80C51XA
80C251
80C251
80198
68HC11
68HC912
Z80
Z8
68330
M37702M2
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
tions.
MCU
8
8
8
8
8
8
8
8
8
8
8
Data Bus
Width
WR
WR
WR
WR
WR
R/W
R/W
WR
R/W
R/W
R/W
CNTL0
RD
RD
PSEN
RD
RD
E
E
RD
DS
DS
E
CNTL1
PSEN
PSEN
(Note
PSEN
(Note
(Note
(Note
(Note
(Note
(Note
(Note
CNTL2
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
1
1
1
1
1
1
1
1
) (Note
) (Note
) (Note
) DBE
) (Note
) (Note
) (Note
) (Note
(Note
(Note
(Note
PC7
1
1
1
1
1
1
1
1
1
1
) ALE
) ALE
) ALE
) ALE
) ALE
) AS
) (Note
) AS
) AS
) ALE
AS
PD0
2
1
) A0
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
ADIO0
(Note
A3-A0
(Note
(Note
(Note
(Note
(Note
D3-D0
(Note
(Note
D3-D0
PA3-PA0
1
1
1
1
1
1
1
1
)
)
)
)
)
)
)
)
(Note
(Note
(Note
(Note
(Note
(Note
(Note
D7-D4
(Note
(Note
D7-D4
PA7-PA3
1
1
1
1
1
1
1
1
1
)
)
)
)
)
)
)
)
)