PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 49

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

Table 20. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, and D. The address input can be
latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is included
in the DPLD equations for the SRAM, or primary or
secondary Flash memory is considered to be an
address input.
Data Port Mode
Port A can be used as a data bus port for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port A if
the port is configured as a Data Port.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A
Figure 23. Peripheral I/O Mode
8051XA (8-bit)
80C251
(Page Mode)
All Other
8-bit Multiplexed
8-bit
Non-Multiplexed Bus
MCU
N/A
N/A
Address a3-a0
N/A
Port A (PA3-PA0)
RD
PSEL0
PSEL1
WR
VM REGISTER BIT 7
1
PSEL
Address a7-a4
N/A
Address a7-a4
N/A
Port A (PA7-PA4)
D0 - D7
DATA BUS
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a 1. Figure 23
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because In-System Programming (ISP) is not per-
formed in normal Operating mode. For more infor-
mation on the JTAG Port, see the section entitled
“PROGRAMMING
JTAG SERIAL INTERFACE”, on page 63.
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (PB3-PB0)
IN-CIRCUIT
PA0 - PA7
N/A
Address a15-a12
Address a7-a4
Address a7-a4
Port B (PB7-PB4)
PSD834F2V
USING
AI02886
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