MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 41

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

INTERFACING OVERVIEW AND CONFIGURATION OPTIONS
accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I
interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I
details for each interface mode follow in this chapter.
SPI INTERFACE
resources of the IC can be controlled. The registers also provide status information about how the IC is operating, as well as
information on external signals.
the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin. With the CS pin held low
during startup (as would be the case if connected to the CS driver of an unpowered processor, due to the integrated pull-down),
the bus configuration will be latched for SPI mode.
addressable register map spans 64 registers of 24 data bits each.
provided in
brevity's sake, references are occasionally made herein to the register set as the “SPI map” or “SPI bits”, but note that bit access
is also possible through the I
accessible by either interface.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 7. SPI / I
Table 8. Register Set
Notes
31.
32.
33.
CS
CLK
MISO
MOSI
The 13892 contains a number of programmable registers for control and communication. The majority of registers are
The 13892 contains a SPI interface port, which allows access by a processor to the register set. Via these registers, the
The SPI interface pins can be reconfigured for reuse as an I
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
The general structure of the register set is given in the following table. Bit names, positions, and basic descriptions are
0
1
2
3
4
5
6
7
8
9
10
11
CS held low at Cold Start configures interface for SPI mode; once activated, CS functions as the SPI Chip Select.
CS tied to VCORE at Cold Start configures interface for I2C mode; the pin is not used in I2C mode other than for configuration.
In I2C mode, the MOSI pin hardwired to ground or VCORE is used to select between two possible addresses.
Pin Name
Interrupt Status 0
Interrupt Mask 0
Interrupt Sense 0
Interrupt Status 1
Interrupt Mask 1
Interrupt Sense 1
Power Up Mode Sense
Identification
Unused
ACC 0
Unused
ACC 1
SPI
Register
Bitmap. Expanded bit descriptions are included in the following functional chapters for application guidance. For
2
C Bus Configuration
2
Configuration
SPI Clock
Master In, Slave Out (data output)
Master Out, Slave In (data input)
C interface option, so such references are implied as generically applicable to the register set
16
17
18
19
20
21
22
23
24
25
26
27
FUNCTIONAL DEVICE OPERATION
SPI Mode Functionality
(31)
Unused
Unused
Memory A
Memory B
RTC Time
RTC Alarm
RTC Day
RTC Day Alarm
Switchers 0
Switchers 1
Switchers 2
Switchers 3
Register
, Chip Select
PROGRAMMABILITY
2
C interface. As a result, a configuration protocol mandates that
32
33
34
35
36
37
38
39
40
41
42
43
Regulator Mode 0
Regulator Mode 1
Power Miscellaneous
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ADC 0
Register
SCL: I
SDA: Bi-directional serial data line
A0 Address Selection
Configuration
2
C bus clock
I2C Mode Functionality
(32)
FUNCTIONAL DEVICE OPERATION
48
49
50
51
52
53
54
55
56
57
58
59
(33)
2
Charger 0
USB0
Charger USB1
LED Control 0
LED Control 1
LED Control 2
LED Control 3
Unused
Unused
Trim 0
Trim 1
Test 0
C interfaces. Further
Register
PROGRAMMABILITY
2
C
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