MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 80

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

FUNCTIONAL DEVICE OPERATION
SUPPLIES
function of how many contiguous SPI clock falling edges are seen while the DVSx pin is held high.
Table 51. SID Control Protocol
its default value of 1.250 V (SW1 = 11010) and is stepped both up and down via the DVS1 pin. The SPI bits SW1 = 11010 do
not change. The set point adjustment takes place in the SID block prior to bit delivery to the switcher's digital control.
recover to its high performance capability with a minimum of communication latency. In
illustrated as an Increment step, initiated by the detection of the second falling SPI clock edge, followed by a continuation to the
programmed SW1[4:0] level (1.250 V in this example), due to the detection of the third contiguous falling edge of SPI clock while
DVS1 is held high.
jog requests will not be stored. For instance, if a switcher is stepping up in voltage with a 25 mV step over a 4.0 μs time, response
to the DVSx pin for another step will be ignored until the DVS step period has expired. However, the Panic Mode step recovery
should respond immediately upon detection of the third SPICLK edge while the corresponding DVSx pin is high, even if the initial
decode of the jog up command is ignored, because it came in before the previous step was completed.
80
13892
Number of SPI CLK Falling
0
1
2
3 or more
When configured for SID mode, a high pulse on the DVSx pin will indicate one of 3 actions to take, with the decoding as a
The SID protocol is illustrated by way of example, assuming SIDEN = 1, and that DVS1 is controlling SW1. SW1 starts out at
SID Panic Mode is provided for rapid recovery to the programmed Normal mode output voltage, so the processor can quickly
The system will not respond to a new jog command until it has completed a DVS step that may be in progress. Any missed
Edges while DVSx = 1
SW1 output
SPICLK
DVS1
SW1 output
SPICLK
DVS1
Starting Value
No action. Switcher stays at its presently programmed configuration
Jog down. Drive buck switcher output down a single DVS step
Jog up. Drive buck switcher output up a single DVS step
Panic Mode. DVS step the buck switcher output to the Normal mode value as programmed in the SPI register
1.250
Figure 21. SID Control Example for Increment & Decrement
Starting Value
Figure 22. SID Control Example for Panic Mode Recovery
1
1.050
Up
1
2
Up
2
DVS
Up
DVS
Up
Panic
3
SPICLK shut down
when not used
SID Panic Mode Example
1.275
DVS step all the way back to 1.250V
(SW1[4:0] programmed value = 1.250V)
Down
1
SPICLK shut down when not used
Function
Down
DVS
1.250
Figure
Analog Integrated Circuit Device Data
Down
1
22, Panic Mode recovery is
Down
DVS
Freescale Semiconductor
1.225