MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 68

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

FUNCTIONAL DEVICE OPERATION
OPERATING MODES
retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected
to PWGTDRV1 (for parallel NMOS switches); SW4 power gating FET drive would typically be connected to PWGTDRV2. When
Low Power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to
isolate the maintained supply domains from any peripheral loading.
gates of external NMOS switches placed between power sources and peripheral loading. The processor core(s) would typically
be connected directly to the SW1 output node so that it can be maintained by SW1, while any circuitry that is not essential for
booting or User Off operation is decoupled via the power gate switch. If multiple power domains are to be controlled together,
power gating NMOS switches can share the PWGT1 gate drive. However, extra gate capacitance may require additional time for
the charge pump gate drive voltage to reach its full value for minimum switch RDS_on.
MEMORY HOLD POWER GATING
the SW4 power domain, to selected circuitry in Low Power modes while cutting off the switcher domain from other peripheral
loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3, are shut down in Memory Hold, so just the
external memory is maintained in self refresh mode.
pin controls the gate of the external NMOS and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold
or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.
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In the typical application, SW1, SW2, and SW3 will all be kept active for the processor modules in state retention, and SW4
The power gate switch driver consist of a fully integrated charge pump (~5.0 V) which provides a low power output to drive the
As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of
An external NMOS is to be placed between the direct-connected memory supply and any peripheral loading. The PWGTDRV2
Figure 13. Power Gating Diagram
Analog Integrated Circuit Device Data
Freescale Semiconductor