MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 110

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Internal Clock Generator (S08ICGV2)
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f
into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f
mode is entered from FLL engaged internal, f
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f
If this mode is entered from off mode, f
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
110
ICGDCLK
ICGDCLK
/ R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
DCOS
COUNTER ENABLE
will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
CLKST
SUBTRACTOR
REFERENCE
DIVIDER (/7)
RANGE
Figure 7-6. Detailed Frequency-Locked Loop Block Diagram
LOCK
MFD
RANGE
OVERFLOW
LOSS OF CLOCK
LOLS
DETECTOR
LOCK AND
LOCS
MC9S08GB60A Data Sheet, Rev. 2
ICGDCLK
ICGIRCLK
ICGDCLK
ERCS
DIGITAL
FILTER
CLKST
LOOP
FLT
ICGDCLK
will default to f
LOCD
will be equal to the frequency of ICGDCLK before
COUNTER
PULSE
will maintain the previous frequency. If this mode
CONTROLLED
ICGIF
OSCILLATOR
FLL ANALOG
DIGITALLY
Self_reset
INTERRUPT
RESET AND
CIRCUIT
SELECT
CLOCK
CONTROL
CLKS
LOLRE LOCRE
ICGDCLK
ICG2DCLK
1x
2x
which is nominally 8 MHz. If this
FREQUENCY
DIVIDER (R)
REDUCED
RFD
Freescale Semiconductor
FREQUENCY-
LOOP (FLL)
LOCKED
ICGOUT
RESET
IRQ