MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 80

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

1
LVWF will be set in the case when V
LVD reset:
Any other
Power-on
Chapter 5 Resets, Interrupts, and System Configuration
5.8.8
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
80
LVWACK
PPDACK
reset:
reset:
LVWF
LVWV
PPDF
PPDC
LVDV
Field
PDC
W
7
6
5
4
3
2
1
0
R
LVWF
System Power Management Status and Control 2 Register (SPMSC2)
0
0
0
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1
to LVWACK clears LVWF to 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.
(1)
7
(1)
(1)
= Unimplemented or Reserved
LVWACK
0
0
0
0
6
Supply
transitions below the trip point or after reset and V
Table 5-11. SPMSC2 Field Descriptions
LVDV
LVD
LVW
LVD
LVW
U
U
0
5
MC9S08GB60A Data Sheet, Rev. 2
= V
= V
= V
= V
LVDL
LVWL
LVDH
LVWH
).
).
).
).
LVWV
U
U
4
0
Description
U = Unaffected by reset
PPDF
0
0
0
3
PPDACK
Supply
0
0
0
0
2
is already below V
Freescale Semiconductor
PDC
0
0
0
1
LVD
LVW
).
).
LVW
PPDC
.
0
0
0
0