MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet
MCIMX255AJM4A
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MCIMX255AJM4A Summary of contents
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... As a result, the i.MX25 enables many of the features only available in high-end systems, but at a price point suitable for all vehicles. At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds 400 MHz. The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs ...
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... On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY. • Fast Ethernet—For rapid external communication, a fast Ethernet controller (FEC) is included. i.MX25 Applications Processor for Automotive Products, Rev Freescale Semiconductor ...
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... MCIMX255AJM4 i.MX251 MCIMX251AJM4A i.MX255 MCIMX255AJM4A 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!) Table 2 shows the functional differences between the different parts in the i ...
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... Yes Yes Yes Yes Yes Yes LCDC / SLCDC ARM Peripherals SSI HS USBOTG HS USB OT GPHY HS USB Host 2 I C(3) FS USB Host PHY CSPI eSDHC(2) ECT ECT IOMUX GPIO(3) GPIO(3) IIM EPIT(2) SCC Timers KPP RTC WDOG GPT(4) Access. Keypad Conn. Freescale Semiconductor ...
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... Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 3. i.MX25 Digital and Analog Modules 1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502. The ARM926 Platform consists of the ARM926EJ-S™ core, the ETM real-time debug modules, a 5x5 Multi-Layer AHB crossbar switch, and a “ ...
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... When the timer is configured to operate in set-and-forget mode capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock internal clock. Freescale Semiconductor ...
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... Shared System control The SPBA controls access to the shared peripherals. It supports shared peripheral bus arbiter i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Brief Description 2 Inter-IC Communication ( industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the 2 interconnection between devices ...
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... Used to select the ARM clock source from MPLL out or from external EXT_ARMCLK. In normal operation, CLK_SEL should be connected to GND. EXT_ARMCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (via muxing) to work as a normal GPIO. ...
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... GND. UPLL_BYPCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (via muxing) to work as a normal GPIO. ...
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... Table 6. DC Operating Conditions NV Table 6. Min. Max. –0.5 1.52 –0.5 3.6 — 2500 — 400 — 200 –0 0.3 DD –40 105 Symbol Min. Typ. Max. QV 1.15 1.34 1. 1.38 1.45 1. 1.15 — 1.55 DD_BAT 1.75 — 3.6 DD_GPIO1 Freescale Semiconductor Units Units ...
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... The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming recommended that FUSE_VDD be connected to ground when not being used for programming. See parameters. 3 NVCC_DRYICE is supply output. A 0.1- F external capacitor should be connected to it. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 6. DC Operating Conditions (continued) Symbol Min. Typ ...
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... Min. Typ. Max — 24 — — 32.768 — 1 Typ. Max. (@Typ. Temp) (@Max. Temp) Rx 11.4 Tx 22,6 Rx 21.5 Tx 33.8 — 0.6 Rx 120 252 Tx 5.5 50 Freescale Semiconductor Units mA mA Units MHz MHz KHz Unit — — mA — — A — A — mA — A — mA 100 A ...
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... USB PLL Off OSC24M On OSC32K On Other modules Off 1 Sleep mode differs from stop mode in that the core voltage is reduced i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 10. i.MX25 Power Mode Settings Power Mode Wait Stop/Sleep Off On Off On On Off ...
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... RTC clock and NOTE Voltage Setting 1. Stop Sleep 3.51 A 3.61 A 0.267 0.32 31.7 A 32.1 1.14 0.871 10.2 mA 10.5 38.9 39.1 842 A 665 A 241 242 0.328 0.231 191 191 164 164 Typical Current Consumption 9.95 A 12.6 A Freescale Semiconductor ...
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... Other power-up sequences may be possible; however, the above sequence has been verified and is recommended. • There is a 1-ms minimum time between supplies coming up, and a 1-ms minimum time between POR_B assert and deassert. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor CAUTION NOTE NOTE 15 ...
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... Common supplies are bundled according to the i.MX25 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX25 power supply requirements are satisfied during startup and transient conditions. Freescale recommends that system current measurements are taken with customer-specific use-cases to reflect the normal operating conditions in the end system ...
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... Refer to The values mentioned above should not be taken as a typical max run data for specific use cases. These values are Absolute MAX data. Freescale recommends that the system current measurements are taken with customer-specific use-cases to reflect normal operating conditions in the end system 3 ...
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... Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection NOTE Symbol Value Unit R 55 °C/W eJA R 33 °C/W eJA R 46 °C/W eJMA R 29 °C/W eJMA R 22 °C/W eJB R 13 °C/W eJCtop 2 °C/W JT Freescale Semiconductor ...
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... Minimum condition: BCS model, 1.95 V, and –40 °C. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: wcs model, 1.65 V, and 105 °C. 3. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: BCS model, 1.95 V, and 105 °C. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Symbol Test Conditions Min. Voh I = – ...
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... V — 0.8 — — 150 nA 80 — — 1180 nA — — 1220 nA Typ. Max. Units — — — 0.28 — — mA — — mA — OVDD + 0.3 — OVDD/2 – 0.125 Freescale Semiconductor Notes — — V — Notes V — — V — ...
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... I/O parameters for GPIO. DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current for slow mode High-level output current for fast mode i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Test Symbol Min. Conditions Vin(dc) — –0.3 Vid(dc) — ...
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... OVDD –0.3 V — 0.3 OVDD 370 — 420 290 320 OVDD — — — — 0.5 OVDD 18 100 120 85 100 120 — — 100 117 — 184 0.0001 0.0001 64 104 0.0001 0.0001 Freescale Semiconductor mA — mA — V — — ...
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... AC Electrical Characteristics This section provides the AC parameters for slow and fast I/O. Figure 3 shows the load circuit for output. propagation waveforms. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Symbol Test Conditions IIN OVDD = 3 OVDD = 3 OVDD = 1 OVDD = 1.8 V IIN OVDD = 3 ...
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... Output (at pad) i.MX25 Applications Processor for Automotive Products, Rev 80% 20% PA1 50% tPLH 80% 50% 20% tTLH 50% tpv 50% Figure 6. Output Enable to Output Valid OVDD 80% 20% 0V PA1 VDD 50% 0V tPHL OVDD 80% 50% 20% 0V tTHL VDD 0 VDD OVDD Freescale Semiconductor ...
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... Output pad propagation tpo delay (high drive), 40%–60% Output pad propagation tpo delay (standard drive), 40%–60% i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 19. Slow I/O AC Parameters Test Min. Capacitance Rise/Fall — — 40 3.0–3 0.95/0.84 3.0– ...
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... Freescale Semiconductor Units Notes V/ns 2 ...
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... Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3 1.95 V (1.65–1.95 V range), and –40 °C. Input transition time from pad (20%–80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 19. Slow I/O AC Parameters (continued) Test Capacitance 3.0– ...
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... V/ns 0.43/0.61 0.72/0.95 0.59/0.81 0.98/1.27 V/ns 0.34/0.50 0.56/0.72 0.40/0.55 0.66/0.87 V/ns 0.23/0.34 0.38/0.52 Freescale Semiconductor — ...
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... Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from pad (20%–80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Test Min. Symbol ...
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... V/ns 0.85/1.24 1.26/1.70 1.19/1.71 1.78/2.39 V/ns 0.63/0.95 0.95/1.30 0.80/1.19 1.20/1.60 V/ns 0.43/0.64 0.63/0.87 Freescale Semiconductor ...
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... Hysteresis mode is recommended for input with transition time greater than 25 ns. 3.6.3 DDR I/O AC Parameters The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see Chapter 4, “External Signals and Pin Multiplexing,” in the i.MX25 Multimedia Applications Processor Reference Manual). i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor 3.6 V (continued) – didt ...
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... Freescale Semiconductor Notes — ...
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... Table 23. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O Parameter Duty cycle Clock frequency Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall tps 25 pF ...
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... V/ns 0.52/0.61 0.90/1.02 0.51/0.63 091/1.06 V/ns 0.36/0.42 0.63/0.67 0.37/0.44 0.65/0.72 V/ns 0.23/0.26 0.39/0.40 Freescale Semiconductor ...
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... AC differential input voltage AC differential cross point voltage for input 3.6.3.2 DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements Table 25 shows AC parameters for SDRAM I/O. Parameter Duty cycle Clock frequency i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall tdit ...
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... V/ns 2 0.92/0.94 1.39/1.30 1.16/1.19 1.76/1.66 V/ns 0.61/0.63 0.93/0.87 0.59/0.60 0.89/0.82 V/ns 0.31/0.32 0.47/0.43 Freescale Semiconductor ...
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... Output pad propagation delay (high drive), 50%–50% input signals and crossing of output signals Output pad propagation delay (standard drive), 50%–50% input signals and crossing of output signals i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall tdit ...
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... V/ns 2 0.93/0.95 1.39/1.29 1.16/1.18 1.76/1.65 V/ns 0.62/0.64 094/0.87 0.59/0.61 0.89/0.83 V/ns 0.31/0.32 0.47/0.43 202 435 mA/ns 3 213 456 135 288 mA/ns 142 302 67 144 mA/ns 70 150 0.11/0.12 0.16/0. 0.87/1.08 1.37/1.62 ns 1.68/1.89 2.18/2.42 Freescale Semiconductor ...
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... Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from pad (20%–80%). i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 27. AC Parameters for DDR2 I/O Load Min ...
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... V/ns 0.72/0.81 1.12/1.16 72 172 400 mA/ns 77 183 422 0.17/0.20 ns 2.16/2.07 ns 2.98/2.88 ns Min. Max. OVDD + 0.3 –0.3 OVDD/2 – 0.25 0.5 OVDD + 0.6 OVDD/2 + 0.175 OVDD/2 + 0.125 Freescale Semiconductor Notes % — — Units ...
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... Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) 1-Wire Tx OW1 Figure 7. 1-Wire RPP Timing Diagram ...
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... Figure 9. Write 1 Sequence Timing Diagram OW8 OW7 OW9 Figure 10. Read Sequence Timing Diagram Table 32. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT t RELEASE Min. Typ. Max. Units 60 100 120 OW5 117 120 Table 32 describes the timing Min. Typ. Max. Units 117 120 15 — 45 Freescale Semiconductor ...
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... Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Maximum difference in cable propagation delay without accounting for ground bounce i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 33. Timing Parameters Description UDMA2,UDMA3 UDMA0,UDMA1,UDMA2,UDMA3,UDMA4 Value/Contributing Factor Peripheral clock frequency ...
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... Figure 11. PIO Read Mode Timing Relation T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew6) T – (tsu + thi) T > tsu + thi + tskew3 + tskew4 trd1 Adjustable Parameter time_1 time_2r time_9 If not met, increase time_2 — time_ax time_pio_rdx time_1, time_2r, time_9 Freescale Semiconductor Table 34 ...
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... Avoid bus contention when switching buffer on by making ton long enough — — Avoid bus contention when switching buffer off by making toff long enough 1 See Figure 12. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor t1 t2w DIOR DIOW ton tA IORDY IORDY Figure 12. PIO Write Mode Timing Relation T – ...
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... Figure 14. MDMA Write Mode Timing Relation T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew6) T – (tskew1 + tskew2 + tskew6 –(tskew1 + tskew2 + tskew5) tk1 tkjn tk1 tkjn toff Table 36 for details Adjustable Parameter(s) time_m time_d time_k time_d, time_k time_d — time_d Freescale Semiconductor ...
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... UDMA in- and out-transfers are provided. 3.7.2.3.1 UDMA In-Transfer Timing Figure 15 shows the timing for UDMA in-transfer start. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Relation T – (tskew1 + tskew2 + tskew6) T – (tsu + tco + 2 T – (tskew1 + tskew2 + tskew6) T – tskew1 T – ...
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... Figure 17. Timing for Device-Terminated UDMA Transfer i.MX25 Applications Processor for Automotive Products, Rev trp tc1 tc1 tx1 tds tdh tzah tzah tli5 tc1 tc1 tss1 tds tdh tzah tzah tack tmli tmli ton tdzfs tcvh toff tack tmli tmli ton tdzfs tcvh toff Freescale Semiconductor ...
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... DMARQ DMACK DIOW DIOR buffer_en DATA WRITE IORDY Figure 18. Timing for UDMA Out-Transfer Start i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 37. Value T) – (tskew1 + tskew2) T) – (tskew1 + tskew2 (tskew1 + tskew2) T – (tskew1 + tskew2 + tskew6) T) – (tco + tsu + tbuf + 2 tcable2) > ...
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... tsui + tco + tbuf + tbuf T – (tskew1) T – (tskew1 + tskew2) T – (tskew1 + tskew2) T) – (tskew1 + tskew2) T – tskew1 T – tskew1 tack tdzfs_mli tcvh toff 38. How to Meet? Freescale Semiconductor time_ack time_env time_dvs time_dvh time_cyc time_cyc — time_dzfs time_ss — — — — time_cvh ...
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... HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted. VSYNC HSYNC PIXCLK DATA[15:0] Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Timing.” Table 39 ...
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... CSI pixel clock high time P6 CSI pixel clock low time P7 CSI pixel clock frequency i.MX25 Applications Processor for Automotive Products, Rev Symbol tV2H tHsu tDsu tDh tCLKh tCLKl fCLK Min. Max. Units 67.5 — — — ns 1.2 — — — ns — 48 10% MHz Freescale Semiconductor ...
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... The values shown in timing diagrams were tested using a worst-case core voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table ...
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... Figure 24. CSPI Slave Mode Timing Diagram Table 41. CSPI Interface Timing Parameters Symbol t7’ t5’ t3’ t2’ t14 t4 t4 t14 Minimum Maximum t 60.2 — clko t 22.65 — clkoH t 22.47 — clkoL t 60.2 — clki t 30.1 — clkiH t 30.1 — clkiL Freescale Semiconductor Units ...
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... ESDCTL Electrical Specifications 3.7.6.1.1 SDRAM Memory Controller The following diagrams and tables specify the timings related to the SDRAMC module which interfaces SDRAM. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Symbol Minimum Maximum 1 t 2.6 8.5 ...
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... Note: CKE is high during the read/write cycle. SD5 Parameter 1 1 SD1 SD2 SD3 SD9 Symbol Min. Max. tCH 3.4 4.1 tCL 3.4 4.1 tCK 7.5 — tCMS 2.0 — tCMH 1.8 — tAS 2.0 — tAH 1.8 — tAC — 6.47 Freescale Semiconductor Unit ...
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... Table 47. SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 26. SDR SDRAM Write Cycle Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Parameter SD1 SD3 SD11 SD5 SD12 SD7 ROW / BA Symbol Min. Max. tOH 1.2 — tRC 10 — ...
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... Max. tCH 3.4 4.1 tCL 3.4 4.1 tCK 7.5 — tCMS 2.0 — tCMH 1.8 — tAS 2.0 — tAH 1.8 — tRP 1 tRCD 1 tDS 2.0 — tDH 1.3 — SD1 SD2 SD3 SD10 ROW/BA Freescale Semiconductor Unit clock 8 clock ns ns ...
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... CKE Don’t care Figure 28. SDRAM Self-Refresh Cycle Timing Diagram The clock continues to run unless CKE is low. Then the clock is stopped in low state. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 44. SDRAM Refresh Timing Parameters Symbol 1 1 SD16 NOTE Min ...
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... SD17 Data Data Data SD17 SD17 SD18 Parameter Min. Max. tCKS 1.8 — SD19 SD20 SD18 Data Data Data Data SD18 1 Symbol Min. tDS 0.95 tDH 0.95 tDSS 1.8 tDSH 1.8 Freescale Semiconductor Unit ns Data DM Max. Unit — ns — ns — ns — ns ...
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... SD23 DQS output access time from SDCLK posedge 3.7.6.1.3 DDR2 SDRAM–Specific Parameters The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with DDR2 SDRAM. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor SD22 SD21 Data Data Data ...
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... Applications Processor for Automotive Products, Rev DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Table Parameter DDR2 49, “tlS, tlH Derating Values for DDR2-400 Symbol Min. Max. t 0.45 0. 0. 0.35 — 0.475 — 0.35 — 0.475 — IH Freescale Semiconductor Unit ...
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... Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor CK, CK Differential Slew Rate 1.5 V/ns tlH tlS tlH +94 +217 +124 +89 +209 +119 +83 +197 +113 +75 +180 ...
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... Max. t 0.025 — DS1(base) t 0.025 — DH1(base) t 0.2 — DSS t 0.2 — DSH t -0.25 0.25 DQSS t 0.35 — DQSH t 0.35 — DQSL Table 1,2,3 0.7 V/ns 0.6 V/ns 0.5 Vns Freescale Semiconductor Unit ns ns tCK tCK tCK tCK tCK 51, “DtDS1, 0.4 V/ ...
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... DDR26 DQS output access time from SDCLK posedge 1 Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor DQS Single-Ended Slew Rate 63 — — ...
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... Applications Processor for Automotive Products, Rev describes the timing parameters (NF1–NF17) that are shown in the figures. NF1 NF3 NF5 NF6 NF8 NF9 Command NF1 NF4 NF3 NF10 NF5 NF7 NF6 NF8 NF9 Address Figure 34 NF2 NF4 NF7 NF11 Freescale Semiconductor through ...
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... Figure 37. Read Data Latch Cycle Timing Diagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... N/A tDHR N/A NOTE Table 54 describes the timing parameters Example Timing for NFC Clock 33 MHz Unit Min. Max. 28 — — — — 27.5 ns 620 — — — ns 12.5 — — — ns Freescale Semiconductor ...
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... BCLK high-level width WE4 Clock fall to address valid WE5 Clock rise/fall to address invalid WE6 Clock rise/fall to CSx_B valid WE7 Clock rise/fall to CSx_B invalid i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor WEIM Output Timing WE1 WE2 ... WE4 WE6 WE8 WE10 WE12 ...
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... Recommended drive strength for all controls, address and BCLK is maximum drive. i.MX25 Applications Processor for Automotive Products, Rev (continued) Parameter NOTE Min. Max. Unit 3 — ns (BCLK/2) + — ns 2.63 6.9 — — ns 2.4 — — ns 7.2 — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
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... Figure 39. Synchronous Memory Timing Diagram for Read Access—WSC=1 BCLK Last Valid Address ADDR CS[x] RW LBA OE EB[y] DATA Figure 40. Synchronous Memory Timing Diagram for Write Access— i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 54 for specific control parameter settings. WE4 V1 WE6 WE14 WE10 WE12 WE19 WE4 V1 ...
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... WE22 WE22 WE19 WE19 V1 V1+2 Halfword Halfword WE18 WE18 WSC=2, SYNC=1, DOL=0 Address V1 WE15 WE24 WE22 WE17 V1 WE16 BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 WE5 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword WE5 WE7 WE9 WE13 WE17 V1+4 V1+8 V1+12 Freescale Semiconductor ...
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... Figure 45 through Figure 49, and state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor WE5 Address V1 Write WE15 WSC=7, LBA=1, LBN=1, LAH=1 WE5 Address V1 ...
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... Figure 46. Asynchronous A/D Muxed Read Access (RWSC = 5) i.MX25 Applications Processor for Automotive Products, Rev WE31 Address V1 WE39 WE35 WE37 V1 WE43 MAXDI WE31 Addr. V1 WE32A WE40 WE39 WE35A WE37 WE32 Next Address WE40 WE36 WE38 WE44 D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
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... LBA OE EB[y] DATA Figure 47. Asynchronous Memory Write Access CS[x] ADDR/ M_DATA RW LBA OE EB[y] Figure 48. Asynchronous A/D Mux Write Access i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 Addr. V1 WE32A WE33 WE40A WE39 ...
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... CSA) –3 + (OEA + 3 + (OEA + RLBN + RLBN + RLBA + RLBA + ADH + 1 – ADH + 1 – CSA) CSA) — 3 – (OEN – CSN) 4 — (RBEA – CSA) 5 — 3 – (RBEN – CSN) — (LBA – CSA) — 3 – CSN Freescale Semiconductor Unit ...
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... DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Determination By Synchronous Measured 1 Parameters WE14 – ...
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... Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. i.MX25 Applications Processor for Automotive Products, Rev first bit Figure 50. ESAI Transmit Timing last bit 88 91 See Note Freescale Semiconductor ...
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... FSR (bit) out FSR (word) out Data in FSR (bit) in FSR (word) in Flags in Figure 52 shows the ESAI HCKT timing diagram. HCKT SCKT (output) i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor first bit Figure 51. ESAI Receive Timing Diagram 95 96 Figure 52. ESAI HCKT Timing ...
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... Table 58. ESAI General Timing Requirements 1 2 Symbol Expression t 4 SSICC 4 — — — 2 — — 2 Table 56 and Table 57 Comments Significance 3 Min. Max. Condition T c 30.0 — 30.0 — — — — 9.0 6 — — 9.0 6 — — Freescale Semiconductor describe Unit ns — ns — — ns — ...
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... SCKT rising edge to FST out (wl) high 83 SCKT rising edge to FST out (wl) low 84 SCKT rising edge to data out enable from high impedance 85 SCKT rising edge to transmitter #0 drive enable assertion i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor 1 2 Symbol Expression — — 5 — 5 — ...
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... C — — 18.0 — — 18.0 Table 59: Freescale Semiconductor Unit — ns — — ns — ns — ns ...
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... In normal-speed mode for MMC card, clock frequency can be any value between MHz. In high speed mode, clock frequency can be any value between MHz satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor SD4 SD2 SD5 CLK ...
Page 84
... FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. i.MX25 Applications Processor for Automotive Products, Rev Table 60 describes the timing parameters (M1–M4) shown Figure 55. MII Receive Signal Timing Diagram Table 60. MII Receive Signal Timing 1 Characteristic M4 Min. Max. Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
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... FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode. 3.7.9.1.3 MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL) Figure 57 shows MII asynchronous input timings. in the figure. FEC_CRS, FEC_COL i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 61 describes the timing parameters (M5–M8) shown Table 61. MII Transmit Signal Timing 1 ...
Page 86
... Applications Processor for Automotive Products, Rev Table 63 M14 M12 M13 Characteristic Min. Max. 1.5 — FEC_TX_CLK period describes the timing parameters M15 M10 M11 Min. Max. 0 — — — 0 — 40% 60% FEC_MDC period 40% 60% FEC_MDC period Freescale Semiconductor Unit Unit ...
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... REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 64 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Figure 59 ...
Page 88
... Table 65. Tx Pin Characteristics Symbol Min — Table 66. Rx Pin Characteristics Symbol Min. 1 0.8 Vcc — OFFTXD ONTXD 0.9V t ONRXD Figure 60. FlexCAN Timing Diagram Typ. Max. Units 1 — Vcc + 0.3 V 0.8 — V Typ. Max. Units 1 — Vcc V 0.4 — 0.5V t OFFRXD Freescale Semiconductor ...
Page 89
... SHDN Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Bus Externally ...
Page 90
... C module timing IC9 IC3 STOP START Standard Mode Fast Mode Min. Max. Min. Max 2.5 4.0 - 0.6 4 3.45 0 0.9 4.0 - 0.6 4.7 - 1.3 4.7 - 0.6 3 250 - 100 4 1000 20+0.1C 300 300 20+0.1C 300 b - 400 - 400 Freescale Semiconductor START Unit ...
Page 91
... A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Parameter ) b Standard Mode Unit Min ...
Page 92
... Wait between HSYNC and VSYNC rising edge T6 Wait between last data and HSYNC rising edge pixel clock period i.MX25 Applications Processor for Automotive Products, Rev Description Table 69 Line n Line 1 T6 Min. Max. 22.5 1000 1 — 5 — 5 — 2 — 1 — Freescale Semiconductor and Unit ...
Page 93
... The output is available at the pulse width modulator output (PWMO) external pin. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor T4 Figure 66. LCDC TFT Mode Timing Diagram Table 70. LCDC TFT Mode Timing Parameters ...
Page 94
... ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816). i.MX25 Applications Processor for Automotive Products, Rev Figure 67. PWM Timing Table 71. PWM Output Timing Parameter Minimum 1 0 12.29 9.91 — — — 8. Maximum ipg_clk — — 0.5 0.5 9.37 — Freescale Semiconductor Unit MHz ...
Page 95
... SIM RST rise time / fall time (SIMx_RSTy) 1 50% duty cycle clock, 2 With With With Cin = 30 pF, Cout = 30 pF, 5 With Cin = 30 pF, i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor 1 /SI1 SI3 SI4 SI5 SI6 Figure 68. SIM Clock Timing Diagram Symbol ...
Page 96
... SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. i.MX25 Applications Processor for Automotive Products, Rev RESPONSE 2 Min. Max. — 200 400 40,000 Units clk cycles clk cycles Freescale Semiconductor ...
Page 97
... SIMx_DATAy_RX_TX is negated • SIMx_SVENy is negated Each of the above steps requires one CKIL period (usually 32 kHz). Power-down may be initiated by a SIM card removal detection may be launched by the processor. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor 3 T1 Min. Max. — 200 ...
Page 98
... SJC timing parameters (SJ1–SJ13) indicated in the SJ1 SJ2 VM VIL Figure 72. Test Clock Input Timing Diagram Min. Max. 0.9 1/Fckil 1.1 1/Fckil 1.8 1/Fckil 2.2 1/Fckil 2.7 1/Fckil 3.3 1/Fckil 0.9 1/Fckil 1.1 1/Fckil SJ2 VM SJ3 Freescale Semiconductor Unit ...
Page 99
... TCK (Input) VIL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 SJ10 Output Data Valid SJ11 SJ10 Output Data Valid Figure 74 ...
Page 100
... V M – i.MX25 Applications Processor for Automotive Products, Rev. 4 100 SJ13 Figure 75. TRST Timing Diagram Table 76. SJC Timing Parameters All Frequencies Min. Max. 1 100 — 40 — — — 50 — — 50 — — 50 — — 44 — 44 100 — 40 — Freescale Semiconductor Unit ...
Page 101
... SDATA (LCD_DATA[7]) RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor tcss tcyc tds MSB trss RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 1, CSPOL = 0) ...
Page 102
... CSPOL=0) trss trsh tcyc tds tdh command data display data (This diagram shows the case CSPOL=1) Typ. Max. Units — — ns — — ns — 2641 ns — — ns — — ns — — ns — — ns — — ns — — ns Freescale Semiconductor ...
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... SS2 AUDn_TXC (Output) AUDn_TXFS (bl) (Output) AUDn_TXFS (wl) (Output) AUDn_TXD (Output) AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 78. SSI Transmitter with Internal Clock Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Min prop ( cyc prop ( cyc prop ( cyc ...
Page 104
... Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pf Freescale Semiconductor ...
Page 105
... SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low SS47 Oversampling clock period i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor SS1 SS5 SS4 SS9 SS11 SS20 SS51 SS47 SS50 ...
Page 106
... Figure 80. SSI Transmitter with External Clock Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 4 106 Parameter SS22 SS25 SS26 SS27 SS31 SS37 SS44 Min. Max. 6.0 — — 3.0 6.0 — — 3.0 Table 81 describes the timing SS24 SS29 SS33 SS39 SS38 SS45 SS46 Freescale Semiconductor Unit ...
Page 107
... SSI. • For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation). i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Parameter External Clock Operation Synchronous External Clock Operation Min ...
Page 108
... External Clock Operation Table 82 describes the timing SS24 SS34 SS41 SS36 Min. Max. 81.4 — 36.0 — — 6.0 36.0 — — 6.0 –10.0 15.0 10.0 — –10.0 15.0 10.0 — — 6.0 — 6.0 10.0 — 2.0 — Freescale Semiconductor Unit ...
Page 109
... With a 250fF load edge (teoc) Valid data out delay after With a 250fF load eoc rise edge (tdata) i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Conditions ADC — Analog Bias — Timing Characteristics — ...
Page 110
... Conditions Power Supply Requirements — — Touchscreen Interface — 3 Conversion Characteristics — Min. Typ. Max. Unit — — 2.1 mA 0.5 mA — — 100 — 1500 — — 10 — +/–0.75 — LSB — +/–2.0 — LSB — — +/–2 %FS Freescale Semiconductor ...
Page 111
... Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Figure 82. Start-up Sequence st ). The best way to guarantee this is to make the input multiplexer ...
Page 112
... ADC operation, including the idle cycles. If the conditions are not met power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again. i.MX25 Applications Processor for Automotive Products, Rev. 4 112 Figure 83. Timing for ADC Normal Operation Freescale Semiconductor ...
Page 113
... Table 84 describes the timing parameter (UA1) shown in the figure. UA1 Start TXD Bit 0 Bit (output) Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor UA1 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Possible Parity Bit ...
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... Possible Parity Bit STOP Bit 7 Bit 6 Par Bit BIT UA2 UA2 Min. Max. 2 – 1/(16 1/F + 1/(16 baud_rate baud_rate baud_rate baud_rate UA4 UA3 Possible Bit 5 Bit 6 Bit 7 Parity Freescale Semiconductor Units — Next Start Bit Units — UA3 STOP BIT Bit ...
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... DAT_SE0 bidirectional, 3-wire mode • DAT_SE0 unidirectional, 6-wire mode • VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode The following subsections describe the timings for these four modes. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Symbol Min 1/F – T TIRbit baud_rate ...
Page 116
... Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode i.MX25 Applications Processor for Automotive Products, Rev. 4 116 Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high US1 US4 US7/US8 Signal Description US2 US6 Freescale Semiconductor ...
Page 117
... USB_VM1 USB_RCV Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Transmit USB_DAT_VP USB_SE0_VM Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Signal Name Direction USB_DAT_VP Out USB_SE0_VM Out USB_TXOE_B Out USB_DAT_VP ...
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... Tx VM data when USB_TXOE_B low In (Rx) • data when USB_TXOE_B high In • Differential Rx data US14 Max. Unit Reference Signal — 5.0 ns — 5.0 ns — 5.0 ns 51.0 % — 8.0 ns — 10.0 ns — 3.0 ns — 3.0 ns — 3.0 ns Signal Description Freescale Semiconductor Condition — USB_TXOE_B USB_TXOE_B ...
Page 119
... US20 Tx rise/fall time US21 Tx duty cycle US22 Tx high overlap US23 Tx low overlap US24 Enable delay US25 Disable delay i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor US4 US2 US5 Signal Name Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — USB_TXOE_B Out — ...
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... Tx VP data when USB_TXOE_B is low Out Tx VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high In Differential Rx data US30 US34 Min. Max. Unit Reference Signal — 3.0 ns — 3.0 ns –4.0 +4.0 ns USB_SE0_VM –6.0 +2.0 ns USB_DAT_VP Signal Description US32 US31 Freescale Semiconductor Condition ...
Page 121
... Tx low overlap US36 Enable delay US37 Disable delay US38 Rx rise/fall time US39 Rx rise/fall time US40 Rx skew US41 Rx skew i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor US38 US40 US39 US41 Signal Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — USB_TXOE_B Out — ...
Page 122
... All dimensions in millimeters. • Dimensioning and tolerancing per ASME Y14.5M-1994. i.MX25 Applications Processor for Automotive Products, Rev. 4 122 Signal Description Table 97 US16 US16 US17 US17 Min. Max. — 6.0 — 0.0 — 9.0 describes the timing Conditions/ Unit Reference Signal Figure 98: Freescale Semiconductor ...
Page 123
... Table 98 Package Ground, Power Sense, and Reference Contact Assignments Contact Name BATT_VDD P10 FUSE_VDD T17 MPLL_GND U17 MPLL_VDD U18 NGND_ADC Y13 NVCC_ADC W13 i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Figure 98 i.MX25 Production Package zzxz Contact Assignment 123 ...
Page 124
... G11, J8, J12, K6, K7, K12, M5, M6, M7, N8, P8, P9 REF V11 UPLL_GND M16 UPLL_VDD L16 USBPHY1_UPLLVDD M17 USBPHY1_UPLLVSS N17 USBPHY1_VDDA K16 USBPHY1_VDDA_BIAS K19 USBPHY1_VSSA L19 USBPHY1_VSSA_BIAS J17 USBPHY2_VDD W18 USBPHY2_VSS W17 i.MX25 Applications Processor for Automotive Products, Rev. 4 124 Contact Assignment Freescale Semiconductor ...
Page 125
... A19 A4 A20 B6 A21 C7 A22 A5 A23 A6 A24 B7 A25 A7 SD0 A12 SD1 C13 SD2 B13 SD3 D14 SD4 D13 i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Contact Signal Name Assignment NFWE_B G4 NFRE_B C1 NFALE F4 NFCLE E4 NFWP_B H4 NFRB C2 D15 J2 D14 J1 D13 H2 D12 H3 D11 ...
Page 126
... VSTBY_REQ R18 VSTBY_ACK T20 POWER_FAIL T19 RESET_B T18 POR_B U19 CLKO V20 BOOT_MODE0 V19 BOOT_MODE1 W20 CLK_SEL W19 TEST_MODE V18 OSC24M_EXTAL Y15 OSC24M_XTAL Y16 OSC32K_EXTAL Y11 OSC32K_XTAL Y10 TAMPER_A N10 TAMPER_B N11 MESH_C P11 MESH_D P12 OSC_BYP Y12 XP V14 Freescale Semiconductor ...
Page 127
... Table 100 Package i.MX25 No Connect Contact Assignments Signal Name NC_BGA_B20 NC_BGA_E17 NC_BGA_H17 NC_BGA_J19 NC_BGA_M18 NC_BGA_P20 NC_BGA_U15 NC_BGA_U16 NC_BGA_V15 NC_BGA_V16 NC_BGA_V17 NC_BGA_W14 NC_BGA_Y2 NC_BGA_Y14 NC_BGA_Y17 i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Contact Signal Name Assignment UART1_RTS T3 UART1_CTS T2 UART2_RXD P4 UART2_TXD T1 UART2_RTS R3 UART2_CTS R2 Contact Assignment B20 ...
Page 128
... Package Ball Map Table 101 shows the i.MX25 17 17 package ball map. i.MX25 Applications Processor for Automotive Products, Rev. 4 128 Table 101. i.MX25 17 17 Package Ball Map Freescale Semiconductor ...
Page 129
... Table 101. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor 129 ...
Page 130
... Table 101. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Automotive Products, Rev. 4 130 Freescale Semiconductor ...
Page 131
... Added • Updated • Updated values in • Updated 0 6/2009 Initial release. i.MX25 Applications Processor for Automotive Products, Rev. 4 Freescale Semiconductor Table 102. Revision History Revision Table 54, "WEIM Bus Timing Parameters," on page 69 Table 6, "DC Operating Conditions," on page 10 Table 1, “Ordering Information,” ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...