MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 51

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.3
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSI and SAP) and external serial interfaces (audio and voice codecs). The AC
timing of AUDMUX external pins is governed by the SSI modules. For more information, see
Section 3.7.17, “Synchronous Serial Interface (SSI)
3.7.4
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
The following subsections describe the CSI timing in gated and ungated clock modes.
3.7.4.1
Figure 20
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on VSYNC, then
HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted.
Freescale Semiconductor
•
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
and
Digital Audio Mux (AUDMUX) Timing
CMOS Sensor Interface (CSI) Timing
Gated Clock Mode Timing
Figure 21
DATA[15:0]
PIXCLK
VSYNC
HSYNC
i.MX25 Applications Processor for Automotive Products, Rev. 4
shows the gated clock mode timings for CSI, and
P1
P3
P2
P4
Timing.”
P5
P7
P6
Table 39
describes the timing
51