MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 53

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.4.2
Figure 22
(P1–P6) that are shown in the figure. In ungated mode the VSYNC and PIXCLK signals are used, and the
HSYNC signal is ignored.
3.7.5
Figure 23
describes the timing parameters (t1–t14) that are shown in the figures. The values shown in timing
diagrams were tested using a worst-case core voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad
voltage of 1.65 V.
Freescale Semiconductor
P1
P2
P3
P4
P5
P6
ID
Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
shows the ungated clock mode timings of CSI, and
and
CSI VSYNC to pixel clock time
CSI DATA setup time
CSI DATA hold time
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
Configurable Serial Peripheral Interface (CSPI) Timing
Ungated Clock Mode Timing
Figure 24
DATA[15:0]
VSYNC
PIXCLK
i.MX25 Applications Processor for Automotive Products, Rev. 4
provide CSPI master and slave mode timing diagrams, respectively.
Table 40. CSI Ungated Clock Mode Timing Parameters
Parameter
P1
P2
P3
tVSYNC
Symbol
tCLKh
tCLKl
fCLK
tDsu
tDh
Table 40
P4
P6
P5
Min.
67.5
1.2
describes the timing parameters
10
10
—
1
48
Max.
—
—
—
—
—
10%
Table 41
Units
MHz
ns
ns
ns
ns
ns
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