MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 52

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MCIMX255AJM4A

Manufacturer Part Number
MCIMX255AJM4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX255AJM4A

Lead Free Status / RoHS Status
Compliant

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52
P1
P2
P3
P4
P5
P6
P7
ID
Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
CSI VSYNC to HSYNC time
CSI HSYNC setup time
CSI DATA setup time
CSI DATA hold time
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
DATA[15:0]
PIXCLK
VSYNC
HSYNC
i.MX25 Applications Processor for Automotive Products, Rev. 4
Parameter
Table 39. CSI Gated Clock Mode Timing Parameters
P1
P3
P2
P4
Symbol
tCLKh
tCLKl
tV2H
fCLK
tHsu
tDsu
tDh
P6
Min.
67.5
1.2
P7
10
10
1
1
P5
48
Freescale Semiconductor
Max.
10%
Units
MHz
ns
ns
ns
ns
ns
ns

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