AD9513BCPZ Analog Devices Inc, AD9513BCPZ Datasheet - Page 19

• Manufacturer Part Number: AD9513BCPZ
• Description: IC CLOCK DIST 3OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9513BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS
• Frequency - Max: 800MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 800MHz
• No. Of Multipliers / Dividers: 3
• No. Of Amplifiers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Package: 32LFCSP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9513/PCBZ - BOARD EVAL CLOCK 3CH AD9513
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 11. Output Delay Full Scale
S0
0
1/3
2/3
1
Table 12. Output Logic Configuration
S1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
Table 13. OUT2 Delay or Phase
S3
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
S4
0
0
0
1/3
1/3
2/3
2/3
1
1
0
1/3
1/3
2/3
2/3
1
1
S2
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
OUT2
Delay
(S0 ≠ 0)
0
1/16
1/8
3/16
1/4
5/16
3/8
7/16
1/2
9/16
5/8
11/16
3/4
13/16
7/8
15/16
OUT0
OFF
CMOS
LVDS
LVDS
CMOS
LVDS
LVDS
CMOS
OFF
OFF
OFF
OFF
LVDS
CMOS
LVDS
CMOS
Delay
Bypass
1.8 ns
6.0 ns
11.6 ns
OUT1
LVDS
CMOS
LVDS
CMOS
CMOS
LVDS
LVDS
CMOS
OFF
OFF
OFF
CMOS
OFF
OFF
OFF
OFF
OUT2
Phase
(S0 = 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT2
OFF
OFF
OFF
OFF
CMOS
LVDS
CMOS
LVDS
OFF
LVDS
CMOS
OFF
CMOS
LVDS
LVDS
CMOS
Rev. 0 | Page 19 of 28
Table 14. OUT2 Divide or OUT1 Phase
S5
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
Table 15. OUT1 Divide or OUT2 Phase
S7
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
Duty cycle is the clock signal high time divided by the total period.
Duty cycle is the clock signal high time divided by the total period.
S6
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S8
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
OUT2
Divide (Duty Cycle
(S2 ≠ 0)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
8 (50%)
9 (44%)
10 (50%)
12 (50%)
15 (47%)
16 (50%)
18 (50%)
24 (50%)
30 (50%)
32 (50%)
OUT1
Divide (Duty Cycle
(S2 ≠ 1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
8 (50%)
9 (44%)
10 (50%)
12 (50%)
15 (47%)
16 (50%)
18 (50%)
24 (50%)
30 (50%)
32 (50%)
1
1
)
)
OUT2 Phase
(S2 = 1 and S0 ≠ 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT1
Phase
(S2 = 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AD9513