AD9513BCPZ Analog Devices Inc, AD9513BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9513BCPZ
• Description: IC CLOCK DIST 3OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9513BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS
• Frequency - Max: 800MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 800MHz
• No. Of Multipliers / Dividers: 3
• No. Of Amplifiers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Package: 32LFCSP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9513/PCBZ - BOARD EVAL CLOCK 3CH AD9513
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9513
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVDS
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS OUTPUTS
CMOS
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
LVDS-TO-CMOS OUT
DELAY ADJUST (OUT2; LVDS AND CMOS)
Output Rise Time, t
Output Fall Time, t
OUT0, OUT1
OUT2
S0 = 1/3
S0 = 2/3
Output Rise Time, t
Output Fall Time, t
OUT0, OUT1, OUT2
OUT0 to OUT1 on Same Part, t
OUT0 to OUT2 on Same Part, t
All LVDS OUTs Across Multiple Parts, t
Same LVDS OUTs Across Multiple Parts, t
All CMOS OUTs on Same Part, t
All CMOS OUTs Across Multiple Parts, t
Same CMOS OUTs Across Multiple Parts, t
Output Skew, t
OUT2
Divide = 1
Divide = 2 − 32
Variation with Temperature
Divide = 1
Divide = 2 − 32
Variation with Temperature
Zero-Scale Delay Time
Full-Scale Time Delay
Zero-Scale Delay Time
Full-Scale Time Delay
Divide = 1
Divide = 2 − 32
Variation with Temperature
Divide = 1
Divide = 2 − 32
Variation with Temperature
Zero-Scale Variation with Temperature
Full-Scale Variation with Temperature
Zero-Scale Variation with Temperature
Full-Scale Variation with Temperature
SKV_C
FC
RC
FL
RL
LVDS
CMOS
3
3
3
3
, CLK-TO-LVDS OUT
, CLK-TO-CMOS OUT
SKV
SKV
SKC
1
1
1
SKV_AB
SKC_AB
SKV_AB
SKC_AB
2
2
2
2
Min
1.03
1.09
1.07
1.13
−135
−205
1.14
1.19
1.20
1.24
−230
Rev. 0 | Page 4 of 28
Typ
200
210
1.29
1.35
0.9
1.35
1.41
0.9
−20
−65
650
650
1.46
1.51
1
1.53
1.57
1
0.35
0.20
1.8
−0.38
0.48
0.31
6.0
−1.3
Max
350
350
1.62
1.68
1.69
1.75
+125
+90
375
300
865
990
1.89
1.94
1.97
2.01
+135
415
330
510
Unit
ps
ps
ns
ns
ps/°C
ns
ns
ps/°C
ps
ps
ps
ps
ps
ps
ns
ns
ps/°C
ns
ns
ps/°C
ps
ps
ps
ps
ns
ps/°C
ns
ps/°C
ns
ps/°C
ns
ps/°C
Test Conditions/Comments
Termination = 100 Ω differential
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT2
B outputs are inverted; termination = open
20% to 80%; C
80% to 20%; C
Everything the same; different logic type
LVDS to CMOS on same part
Delay off on OUT2
Delay off on OUT2
Delay off on OUT2
LOAD
LOAD
= 3 pF
= 3 pF