ICS85105AGILF IDT, Integrated Device Technology Inc, ICS85105AGILF Datasheet - Page 10

• Manufacturer Part Number: ICS85105AGILF
• Description: IC FANOUT BUFFER HCSL 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85105AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: HCSL
• Frequency - Max: 500MHz
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 500MHz
• Number Of Clock Inputs: 2
• Output Frequency: 500MHz
• Output Logic Level: HCSL
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1152; 800-1152-5; 800-1152; 85105AGILF

F
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
and V
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
F
F
IDT
IGURE
IGURE
IGURE
IFFERENTIAL
ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
™
2.5V
/ ICS
HCSL
CMR
3.3V
3C. H
3A. H
3E. H
*Optional – R3 and R4 can be 0
1.8V
™
input requirements. Figures 3A to 3F show interface
LVPECL
0.7V HCSL FANOUT BUFFER
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
D
D
H
D
*R3
*R4
I
RIVEN BY A
I
RIVEN BY AN
I
I
RIVEN BY A
P
P
P
P
C
ER
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
C
33
33
C
C
C
LOCK
LOCK
LOCK
LOCK
I
NPUT
Zo = 50
Zo = 50
S CLK/nCLK I
3.3V LVPECL D
S CLK/nCLK I
S LVHSTL D
3.3V HCSL D
S CLK/nCLK I
IDT O
R1
50
3.3V
R3
125
I
NTERFACE
R1
84
R1
50
PEN
R2
50
R4
125
R2
84
E
MITTER
RIVER
CLK
nCLK
R2
50
RIVER
NPUT
NPUT
CLK
nCLK
NPUT
3.3V
RIVER
3.3V
CLK
nCLK
HiPerClockS
Input
HiPerClockS
Input
3.3V
HiPerClockS
Input
PP
10
F
F
F
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
IGURE
IGURE
IGURE
2.5V
3.3V
3.3V
SSTL
3B. H
LVDS_Driv er
3F. H
3D. H
LVPECL
D
D
D
I
RIVEN BY A
I
RIVEN BY A
I
RIVEN BY A
P
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
ER
Zo = 60
Zo = 60
C
C
C
LOCK
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL D
S CLK/nCLK I
2.5V SSTL D
3.3V LVDS D
S CLK/nCLK I
S CLK/nCLK I
R1
50
R3
50
R3
120
2.5V
ICS85105AGI REV. A JUNE 5, 2008
R1
120
R2
50
R1
100
R4
120
CLK
nCLK
R2
120
3.3V
RIVER
RIVER
NPUT
NPUT
NPUT
HiPerClockS
RIVER
Input
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Receiv er