ICS85105AGILF IDT, Integrated Device Technology Inc, ICS85105AGILF Datasheet - Page 6

• Manufacturer Part Number: ICS85105AGILF
• Description: IC FANOUT BUFFER HCSL 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85105AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: HCSL
• Frequency - Max: 500MHz
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 500MHz
• Number Of Clock Inputs: 2
• Output Frequency: 500MHz
• Output Logic Level: HCSL
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1152; 800-1152-5; 800-1152; 85105AGILF

IDT
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
A
O
DDITIVE
FFSET
F
ROM
P
C
HASE
6
ARRIER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
J
F
ITTER
REQUENCY
12kHz - 20MHz at 100MHz = 0.22ps (typical)
Additive Phase Jitter,
(H
Z
)
ICS85105AGI REV. A JUNE 5, 2008
Integration Range: