LMX2541SQE3320E/NOPB National Semiconductor, LMX2541SQE3320E/NOPB Datasheet - Page 42

• Manufacturer Part Number: LMX2541SQE3320E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE3320E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE3320ETR

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2.4 REGISTER R4
This register controls miscellaneous functions of the device. The action of programming the R4 register also synchronizes the VCO
divider, which is necessary when VCO_DIV = 4 or 5.
OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking
This word is used for the VCO frequency calibration. This word should be set to the OSCin frequency rounded to the nearest MHz.
VCO_DIV[5:0] - VCO Divider
The output of the VCO is divided by the value of VCO_DIV, which can range from 1 (Bypass Mode) to 63 and all values in between
with the limitation that the VCO divider can only be set to bypass mode when the device is operating in full chip mode. When the
VCO divider is set to 4 or 5 ONLY, there is one extra programming step required to synchronize the VCO divider. Consult the
functional description for more details.
R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3
This word controls the state of the internal loop filter resistor R3_LF when the device is in Full Chip Mode and Fastlock is not active.
R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4
This word controls the state of the internal loop filter resistor R4_LF when the device is in Full Chip Mode and Fastlock is not active.
VCO_DIV
62
63
...
0
1
2
3
4
5
6
VCO Output Divide
Bypass Mode
R3_LF Value
Divide by 62
Divide by 63
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
5-7
n/a
...
0
1
2
3
4
OSC_FREQ
255
...
0
1
2
Extra programming is required for divide by 4 and divide by 5 only.
This state only available for MODE=Full Chip Mode
Refer to the functional description for more details.
42
R3 Resistor During Fastlock (kΩ)
OSCin Frequency
Low ( 200 Ω )
Illegal State
and higher
Reserved
255 MHz
1 MHz
2 MHz
16
...
1
2
4
Illegal State
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