SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 240

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

240
Offset 04h-05h
The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[9].
Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 06h.
15:6
Bit
1
0
5
4
3
2
1
Description
SMI Source is Audio Subsystem. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the
audio subsystem.
0: No.
1: Yes.
The second level of status is found in F3BAR0+Memory Offset 10h/12h.
SMI Source is Power Management Event. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was
caused by one of the power management resources (except for GP timers, UDEFx and PCI/ISA function traps which are
reported in bit 9).
0: No.
1: Yes.
The next level (second level) of SMI status is at F0 Index 84h/F4h-87h/F7h.
Reserved.
PCI/ISA Function Trap. Indicates whether or not an SMI was caused by a trapped PCI/ISA configuration cycle.
0: No.
1: Yes.
To enable SMI generation for:
SMI Source is Trapped Access to User Defined Device 3. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 3 (F0 Index C8h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[6] = 1.
SMI Source is Trapped Access to User Defined Device 2. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 2 (F0 Index C4h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[5] = 1.
SMI Source is Trapped Access to User Defined Device 1. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 1 (F0 Index C0h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[4] = 1.
SMI Source is Expired General Purpose Timer 2. Indicates whether or not an SMI was caused by the expiration of Gen-
eral Purpose Timer 2 (F0 Index 8Ah).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[1] = 1.
—
—
—
—
—
—
Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.
Trapped access to F1 register space set F0 Index 41h[1] = 1.
Trapped access to F2 register space set F0 Index 41h[2] = 1.
Trapped access to F3 register space set F0 Index 41h[3] = 1.
Trapped access to F4 register space set F0 Index 41h[4] = 1.
Trapped access to F5 register space set F0 Index 41h[5] = 1.
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
32579B
Second Level General Traps & Timers
PME/SMI Status Mirror Register (RO)
Core Logic Module - SMI Status and ACPI Registers - Function 1
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 0000h