SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 300

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

300
I/O Port 0D2h
Note:
I/O Port 0D4h
Note:
I/O Port 0D6h
Note:
I/O Port 0D8h
Note:
I/O Port 0DAh
Note:
I/O Port 0DCh
Note:
Bit
7:3
1:0
7:3
1:0
7:6
3:2
1:0
2
2
5
4
Channels 5, 6, and 7 are not supported.
Channels 5, 6, and 7 are not supported.
Channels 5, 6, and 7 are not supported.
Channels 5, 6, and 7 are not supported.
Channels 5, 6, and 7 are not supported.
Channels 5, 6, and 7 are not supported.
Description
Reserved. Must be set to 0.
Request Type.
0: Reset.
1: Set.
Channel Number Request Select.
00: Illegal.
01: Channel 5.
10: Channel 6.
11: Channel 7.
Reserved. Must be set to 0.
Channel Mask.
0: Not masked.
1: Masked.
Channel Number Mask Select.
00: Channel 4.
01: Channel 5.
10: Channel 6.
11: Channel 7.
Transfer Mode.
00: Demand.
01: Single.
10: Block.
11: Cascade.
Address Direction.
0: Increment.
1: Decrement.
Auto-initialize.
0: Disabled
1: Enable
Transfer Type.
00: Verify.
01: Write transfer (I/O to memory).
10: Read transfer (memory to I/O).
11: Reserved.
Channel Number Mode Select.
00: Channel 4.
01: Channel 5.
10: Channel 6.
11: Channel 7.
Channel 4 must be programmed in cascade mode. This mode is not the default.
32579B
Table 6-43. DMA Channel Control Registers (Continued)
DMA Clear Mask Register Command, Channels 7:4 (W)
DMA Clear Byte Pointer Command, Channels 7:4 (W)
Software DMA Request Register, Channels 7:4 (W)
DMA Channel Mode Register, Channels 7:4 (WO)
DMA Channel Mask Register, Channels 7:4 (WO)
DMA Master Clear Command, Channels 7:4 (W)
AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - ISA Legacy Register Space