SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 44

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

3.2
Several balls are read at power-up that set up the state of
the SC1200/SC1201 processor. These balls are typically
multiplexed with other functions that are outputs after the
power-up sequence is complete. The SC1200/SC1201 pro-
cessor must read the state of the balls at power-up and the
internal PU or PD resistors do not guarantee the correct
state will be read. Therefore, it is required that an external
44
Strap Option Muxed With
CLKSEL0
CLKSEL1
CLKSEL2
CLKSEL3
BOOT16
TFT_PRSNT
LPC_ROM
FPCI_MON
DID0
DID1
Note:
Accuracy of internal PU/PD resistors: 80K to 250K.
Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC1200/SC1201
Processor Specification Update document.
Strap Options
RD#
SOUT1
SOUT2
SYNC
ROMCS#
SDATA_OUT
PCICLK1
PCICLK0
GNT0#
GNT1#
32579B
Ball No.
AF3
D29
P30
P29
C8
D6
C5
C6
B8
A4
PU or PD
Nominal
Internal
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
100
100
100
100
100
100
100
100
100
100
Table 3-4. Strap Options
See Table 4-7 on page 85 for
CLKSEL strap options.
Enable boot
from 8-bit ROM
TFT not muxed
onto Parallel
Port
Disable boot
from ROM on
LPC bus
Disable Fast-
PCI, INTR_O,
and SMI_O
monitoring sig-
nals.
Defines the system-level chip ID.
External PU/PD Strap Settings
Strap = 0 (PD)
PU or PD resistor with a value of 1.5 KΩ be placed on the
balls listed in Table 3-4. The value of the resistor is impor-
tant to ensure that the proper state is read during the
power-up sequence. If the ball is not read correctly at
power-up, the SC1200/SC1201 processor may default to a
state that causes it to function improperly, possibly result-
ing in application failure.
Enable boot
from 16-bit
ROM
TFT muxed
onto Parallel
Port
Enable boot
from ROM on
LPC bus
Enable Fast-
PCI, INTR_O,
and SMI_O
monitoring sig-
nals. (Useful
during debug.)
Strap = 1 (PU)
AMD Geode™ SC1200/SC1201 Processor Data Book
Register References
GCB+I/O Offset 1Eh[9:8] (aka CCFC register
bits [9:8]) (RO): Value programmed at reset
by
CLKSEL[1:0].
GCB+I/O Offset 10h[3:0] (aka MCCM regis-
ter bits [3:0]) (RO): Value programmed at
reset by
CLKSEL[3:0].
GCB+I/O Offset 1Eh[3:0] (aka CCFC register
bits [3:0]) (R/W, but write not recommended):
Value programmed at reset by CLKSEL[3:0].
Note: Values for GCB+I/O Offset 10h[3:0]
and 1Eh[3:0] are not the same.
GCB+I/O Offset 34h[3] (aka MCR register bit
3) (RO): Reads back strap setting.
GCB+I/O Offset 34h[14] (R/W): Used to allow
the ROMCS# width to be changed under pro-
gram control.
GCB+I/O Offset 30h[23] (aka PMR register
bit 23) (R/W): Reads back strap setting.
F0BAR1+I/O Offset 10h[15] (R/W): Reads
back strap setting and allows LPC ROM to be
changed under program control.
GCB+I/O Offset 34h[30] (aka MCR register
bit 30) (RO): Reads back strap setting.
Note:
GCB+I/O Offset 34h[31,29] (aka MCR regis-
ter bits 31 and 29) (RO): Reads back strap
setting.
Note:
For normal operation, strap this sig-
nal low using a 1.5 KΩ resistor.
These signals should be connected
to a 1.5 KΩ PD resistor to ensure a
low level at power-up.
Signal Definitions