PEB20571FV3.1XT Infineon Technologies, PEB20571FV3.1XT Datasheet - Page 125

• Manufacturer Part Number: PEB20571FV3.1XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV3.1XT

• Lead Free Status / Rohs Status: Compliant

Figure 36
Figure 42
4.4.1.5
The incoming serial data is converted into parallel bytes, and stored in the I-buffer input
blocks. The sequence for every time slot received is from MSB (bit 7) to LSB (bit 0).
Transmission is performed from MSB (bit 7) to LSB (bit 0).
4.4.1.6
The data read from the PCMU frame buffers by the DSP always reside in the low byte of
the 16-bit word. The high byte of the read word is driven by the 8-bit PCMU Data Prefix
Register (PDPR). The data prefix is used to accelerate the A-/µ-law to linear conversions
(refer to
Any octet written by the DSP to any location in the PCMU frame buffers should reside in
the low byte (8 LSB). The high byte of the written word is “don’t care”.
Data Sheet
PFS
PDC
TXD
RXD
PFS
PDC
TXD
RXD
Chapter
TS31
shows the PCM interface timing with single and double rate PDC.
bit0
PCMU Serial Data Processing
PCMU Parallel Data Processing
TS31
TS31
TS31
bit0
bit0
IOM-2 Interface Timing in Single/Double Clock Mode
bit0
4.5).
Frame Start
Frame Start
TS0
bit7
TS0
bit7
= data Sampling
TS0
bit7
TS0
TS0
bit6
bit7
TS0
bit6
TS0
bit5
TS0
bit5
TS0
bit6
108
TS0
TS0
bit4
bit6
TS0
bit4
Double Data Rate PDC
Single Data Rate PDC
TS0
bit3
TS0
bit3
= PFS Sampling
TS0
bit5
TS0
TS0
bit2
bit5
TS0
bit2
Functional Description
TS0
bit1
TS0
bit1
TS0
bit4
TS0
TS0
bit0
bit4
TS0
bit0
PEB 20570
PEB 20571
2003-07-31
TS1
bit7
TS1
bit7