PEB20571FV3.1XT Infineon Technologies, PEB20571FV3.1XT Datasheet - Page 94

• Manufacturer Part Number: PEB20571FV3.1XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV3.1XT

• Lead Free Status / Rohs Status: Compliant

Figure 22
Up Coding (in VIP)
The coding technique used on the Up interface is a half-bauded AMI code (with a 50 %
pulse width (refer to
are coded as alternate positive and negative pulses. Code violation (CV) is caused by
two successive pulses with the same polarity.
The AMI coding includes always the data bits going on the Up interface in one direction.
Consequently there is a separate AMI coding unit for data from the DELIC to the VIP
implemented in the VIP, and vice versa.
Data Sheet
TE/PT
LT
t
d
LF
1
U
PN
B1
8
Interface Frame Structure
Figure
1)
2)
23). A logical ‘0’ corresponds to a neutral level, logical ‘1’s
M Channel Superframe
CV = Code Violation: for Superframe synchronization
T = Transparent Channel (2 kbit/s)
S = Service Channel (1 kbit/s)
DC balancing bit, only sent after a code violation in the
M-bit position and in special configurations.
Timings:
B2
8
t
t
t
t
g
r
d
g
= burst repetition period = 250
= ine delay = 20.8
= guard time = 5.2
t
r
LF-Framing Bit
77
99 s
D
4
s
s
maximum
CV T S T CV T S T CV
minimum
B1
8
s
t
d
Functional Description
B2
8
PEB 20570
PEB 20571
ITD00823
2003-07-31
M DC
1 #Bits
1
)
2)