PEB20571FV3.1XT Infineon Technologies, PEB20571FV3.1XT Datasheet - Page 224

PEB20571FV3.1XT

Manufacturer Part Number
PEB20571FV3.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20571FV3.1XT

Lead Free Status / Rohs Status
Compliant
6.2.6.9
GASYNC Register
Reset value: 0000
Accesses to register GASYNC:
IOPORT
bits
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Accesses to the different bits of this register are only possible in ASYNC mode of the
corresponding GHDLC channel (See “GHDLC Mode Registers” on page 204.).
Note: GHDLC channels 3,2,1 are only accessible, if the respective bits in register
Data Sheet
MUXCTRL are set.
15
7
x
Writing a "1" to the bit position
sets the port pin below
LTXD0
LTXD1
LTXD2
LTXD3
LRTS0
LRTS1
LRTS2
LRTS3
ASYNC Control Register
14
x
6
13
x
5
IOPORT(7..0)
12
read/ write
x
4
207
Reading from the bit position indicates the
current state of the port pin below
LRXD0
LRXD1
LRXD2
LRXD3
LCTS0
LCTS1
LCTS2
LCTS3
11
x
3
10
x
2
Register Description
Address: D0D2
9
x
1
PEB 20570
PEB 20571
2003-07-31
8
0
x
H

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