PEB20570FV31XP Lantiq, PEB20570FV31XP Datasheet - Page 134

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Lantiq

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

In receive direction, the processor fetches the D-channel (16 kbit/s signalling) or the B-
channel (64 kbit/s) from the assigned timeslot and writes it into the corresponding
channel register of the HDLC Unit. After the HDLC Unit encoded the data (e.g.
performed bit stuffing), the processor reads ready data and stores it in the receive buffer
in on-chip memory. The data flow is shown in the following figure.
Figure 45
The Receive Input and Receive Output Buffers within the HDLCU are 1 Byte per HDLC
channel. The main Rx Buffer in DSP RAM is 2 x 8-Byte large per HDLC channel (in the
DELIC-LC version).
Data Sheet
IOM-2 / PCM
HDLC Data Flow in Receive Direction
DP RAM with
IOM-2 or PCM
structure
DELIC
("O", Flag, CRC)
Channel_n
S/P
HDLC
HDLC Unit
D
D
DP RAM
MON
MON
B1
B2
C/I
B1
B2
C/I
Receive
Receive
Output
Buffer
Buffer
Input
M
M
117
1.
2.
Maibox
µP
DSP
3.
Functional Description
e.g. 8 Byte
e.g. 8 Byte
DSP Data
Rx Buffer
Rx Buffer
Memory
Page 1
Page 2
PEB 20570
PEB 20571
HDLC-RX
2003-07-31