PEB20570FV31XP Lantiq, PEB20570FV31XP Datasheet - Page 55

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Lantiq

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

2.5
Table 19
Pin No.
DREQR
(11)
DSP_STOP
(63)
DCL (40):
TSC3 (83):
TSC2 (81)
DREQT
(10)
Data Sheet
Strap Pin Definitions
Strap Name Strap Function
CLOCK
MASTER
BOOT
TEST(2)
TEST(1)
TEST(0)
EMULATION
BOOT
Strap Pins (Evaluated During Reset)
0: (default)
1:
0: (default)
1:
111:
(default)
101
100
011
010
001
110
0: (default)
1:
Clock Slave
PDC and PFS are used as inputs.
PDC = 2.048 MHz
PFS = 4 kHz
Clock Master
PDC and PFS are used as outputs.
PDC = 2.048 MHz
PFS = 8 kHz
The DSP starts running from address FFFE
and executes the µP boot routine.
The DSP starts running directly from address
0000
Regular Work Mode
Test mode 1
Test mode 2
Test mode 3
Test mode 4
Test mode 5
undefined
After reset the boot-routine loads the program
RAM via the P-interface (via the general
mail-box).
After reset the boot-routine loads
the program RAM via the CDI mail-box (via
the JTAG interface).
38
H
. The boot routine is not executed.
Pin Description
PEB 20570
PEB 20571
2003-07-31
H
,