MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 25

• Manufacturer Part Number: MCC501RX200TD0B
• Manufacturer: Freescale Semiconductor

Specifications of MCC501RX200TD0B

• Package Type: BGA
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

External Mode
Queue Management Unit
simultaneously supports multiple application-defined tables and multiple search
strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.
The C-5 NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules
(at frequencies to 133MHz) for storage of its tables. These modules allow implementation
of tables with 2
SRAM technology. The maximum amount of memory supported by the TLU is 32MBytes
in four banks.
Table 4 TLU SRAM Configurations
*
There is support for external devices. Refer to the C-5 Archictecture Guide.
The Queue Management Unit (QMU) autonomously manages a number of
application-defined descriptor queues. It handles inter-CP and inter-C-5 NP descriptor
flows by providing switching and buffering. It also performs descriptor replication for
multicast applications. A number of queues can be assigned to each CPRC for QoS-based
services.
The QMU provides a queuing engine internal to the chip and uses external SRAM to store
the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and
16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor” ,
which is a structure that defines the payload buffer handle and other attributes of the
forwarded cell or packet.
The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single
bank of up to 128k, 32bit words. This interface runs at half (
SRAM TECHNOLOGY*
1Mbit (32k x 32)
2Mbit (64k x 32)
4Mbit (256k x 18)
8Mbit (512k x 18
16Mbit (1M x 18)
For (n x 32) parts, divide total memory and number of parts by two.
20
x 64bit entries at a cycle time of up to 7.5 nanoseconds using 4Mbit
MIN TABLE SIZE
(ONE BANK)
256kBytes
512kBytes
2MBytes
4MBytes
8MBytes
NO. OF
PARTS
2
2
4
4
4
MAXIMUM TABLE SIZE
(FOUR BANKS)
1MBytes
2MBytes
8MBytes
16MBytes
32MBytes
1
/
2
) the core clock frequency.
External Mode
NO. OF
PARTS
8
8
16
16
16
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