MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 42

• Manufacturer Part Number: MCC501RX200TD0B
• Manufacturer: Freescale Semiconductor

Specifications of MCC501RX200TD0B

• Package Type: BGA
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

42
C5NP
CHAPTER 2: SIGNAL DESCRIPTIONS
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Figure 4 PROM Interface Diagram
The PROM interface operates in the following manner:
Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in
Figure
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
PROM _Return_Data
presentation register.
PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift
register.
presentation register and the first PROM_DATA into the external shift register.
processor internal shift register.
PROM _H_Word
5.
31
PROM_ADDR<21:1>
21
21
C-5 Network Processor
PROM _LO_Word
16
PROM Sequencer
PROM Clock Gen.
15
15
21
Internal Shift
Register
6
CE
0
1
0
0
SPCLK
SPLD
SPDO
SPDI
External Logic
21
21
PROM_ADDR<21:1>
21
External Shift Register
PROM
6 0
0
1
PROM_Data
16
CE