LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 122

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
BITS
1-0
5
4
3
2
Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the
transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the
transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time
is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and
then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When
reset, the deferral check is disabled in the MAC and the MAC defers indefinitely.
Reserved
Transmitter enable (TXEN). When set, the MAC’s transmitter is enabled and it will transmit frames
from the buffer onto the cable.
When reset, the MAC’s transmitter is disabled and will not transmit any frames.
Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from
the internal PHY.
When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY.
Reserved
DATASHEET
122
DESCRIPTION
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
SMSC LAN9118
Datasheet