LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 154

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
7.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 7.2 LAN9118 PIO Burst Read Cycle Timing
Table 7.4 PIO Burst Read Timing
DATASHEET
154
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9118
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns