LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 82

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
6.3
Base Address +
Offset
ACh
5Ch
6Ch
7Ch
8Ch
9Ch
50h
54h
58h
60h
64h
68h
70h
74h
78h
80h
84h
88h
90h
94h
98h
A0h
A4h
A8h
B0h
B4h
The table below, lists the registers that are directly addressable by the host bus.
System Control and Status Registers
MAC_CSR_DATA
MAC_CSR_CMD
RX_FIFO_INF
TX_FIFO_INF
RX_DP_CTL
Table 6.1 LAN9118 Direct Address Register Map
BYTE_TEST
RESERVED
RESERVED
FREE_RUN
PMT_CTRL
GPIO_CFG
E2P_DATA
RX_DROP
GPT_CFG
E2P_CMD
GPT_CNT
AFC_CFG
IRQ_CFG
FIFO_INT
HW_CFG
INT_STS
RX_CFG
TX_CFG
ENDIAN
ID_REV
INT_EN
Symbol
Control and Status Registers
DATASHEET
REGISTER NAME
Chip ID and Revision.
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
ENDIAN
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
82
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
See “ID_REV—
Revision” on
Chip ID and
0000FFFFh
0000FFFFh
00000000h
00000000h
00000000h
87654321h
48000000h
00000000h
00000000h
00000800h
00000000h
00000000h
00001200h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
SMSC LAN9118
page 84.
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Datasheet